TermComp 2020: Runtime_Complexity: TRS Certified 41529 Job info CSV Showing results.

tct-trs_v3.2.0_2020-06-28
benchmark UPLOWTIME
Various_04/04.xml 11774044 u ∞ +0 1 +0 0.17/0.18
Various_04/08.xml 11774037 u ∞ +0 1 +0 0.26/0.19
Various_04/10.xml 11774038 u timeout (wallclock)
Various_04/11.xml 11774035 u ∞ +0 1 +0 9.57/3.25
Various_04/12.xml 11774043 u ∞ +0 1 +0 1182.60/296.26
Various_04/13.xml 11774040 u ∞ +0 1 +0 841.16/296.36
Various_04/14.xml 11774041 u ∞ +0 1 +0 811.49/296.15
Various_04/15.xml 11774042 s n1 +1 1 +0 0.04/0.07
Various_04/18.xml 11774036 u ∞ +0 1 +0 0.05/0.08
Various_04/22.xml 11774039 u ∞ +0 1 +0 10.21/4.19
Various_04/23.xml 11774033 u ∞ +0 1 +0 0.06/0.14
Various_04/24.xml 11774034 u ∞ +0 1 +0 98.65/53.81
Transformed_CSR_04/Ex14_AEGL02_C.xml 11774210 u ∞ +0 1 +0 956.09/296.13
Transformed_CSR_04/Ex14_AEGL02_FR.xml 11774472 u ∞ +0 1 +0 101.23/44.91
Transformed_CSR_04/Ex14_AEGL02_GM.xml 11774245 u ∞ +0 1 +0 145.31/84.03
Transformed_CSR_04/Ex14_AEGL02_L.xml 11774287 u ∞ +0 1 +0 19.37/8.06
Transformed_CSR_04/Ex14_AEGL02_Z.xml 11774469 u ∞ +0 1 +0 28.67/11.24
Transformed_CSR_04/Ex14_Luc06_C.xml 11774323 u ∞ +0 1 +0 0.07/0.09
Transformed_CSR_04/Ex14_Luc06_GM.xml 11774574 u ∞ +0 1 +0 0.06/0.08
Transformed_CSR_04/Ex15_Luc06_C.xml 11774396 s n1 +1 1 +0 0.08/0.08
Transformed_CSR_04/Ex15_Luc06_FR.xml 11774333 s n1 +1 1 +0 0.12/0.09
Transformed_CSR_04/Ex15_Luc06_GM.xml 11774592 s n1 +1 1 +0 0.07/0.04
Transformed_CSR_04/Ex15_Luc06_L.xml 11774536 u ∞ +0 1 +0 19.75/8.06
Transformed_CSR_04/Ex15_Luc06_Z.xml 11774233 s n1 +1 1 +0 0.14/0.06
Transformed_CSR_04/Ex15_Luc98_C.xml 11774399 u ∞ +0 1 +0 839.05/296.54
Transformed_CSR_04/Ex15_Luc98_FR.xml 11774582 u ∞ +0 1 +0 53.12/20.62
Transformed_CSR_04/Ex15_Luc98_GM.xml 11774351 s n1 +1 1 +0 4.41/1.34
Transformed_CSR_04/Ex15_Luc98_L.xml 11774537 u ∞ +0 1 +0 0.00/0.02
Transformed_CSR_04/Ex15_Luc98_Z.xml 11774257 u ∞ +0 1 +0 40.83/15.23
Transformed_CSR_04/Ex16_Luc06_C.xml 11774361 u ∞ +0 1 +0 0.04/0.04
Transformed_CSR_04/Ex16_Luc06_GM.xml 11774560 u ∞ +0 1 +0 0.04/0.08
Transformed_CSR_04/Ex16_Luc06_L.xml 11774238 u ∞ +0 1 +0 19.11/8.09
Transformed_CSR_04/Ex18_Luc06_C.xml 11774453 s n1 +1 1 +0 0.05/0.03
Transformed_CSR_04/Ex18_Luc06_FR.xml 11774270 s n1 +1 1 +0 0.12/0.05
Transformed_CSR_04/Ex18_Luc06_GM.xml 11774450 s n1 +1 1 +0 0.10/0.05
Transformed_CSR_04/Ex18_Luc06_Z.xml 11774193 s n1 +1 1 +0 0.06/0.09
Transformed_CSR_04/Ex1_2_AEL03_C.xml 11774347 u ∞ +0 1 +0 905.00/296.17
Transformed_CSR_04/Ex1_2_AEL03_FR.xml 11774408 u ∞ +0 1 +0 65.00/28.77
Transformed_CSR_04/Ex1_2_AEL03_GM.xml 11774204 u ∞ +0 1 +0 709.64/296.11
Transformed_CSR_04/Ex1_2_AEL03_L.xml 11774274 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/Ex1_2_AEL03_Z.xml 11774517 u ∞ +0 1 +0 85.60/39.59
Transformed_CSR_04/Ex1_2_Luc02c_C.xml 11774533 u timeout (wallclock)
Transformed_CSR_04/Ex1_2_Luc02c_FR.xml 11774265 u ∞ +0 1 +0 95.53/47.27
Transformed_CSR_04/Ex1_2_Luc02c_GM.xml 11774457 u ∞ +0 1 +0 250.88/152.96
Transformed_CSR_04/Ex1_2_Luc02c_L.xml 11774394 u ∞ +0 1 +0 0.01/0.06
Transformed_CSR_04/Ex1_2_Luc02c_Z.xml 11774355 s n1 +1 1 +0 0.40/0.14
Transformed_CSR_04/Ex1_GL02a_C.xml 11774353 u ∞ +0 1 +0 815.35/296.41
Transformed_CSR_04/Ex1_GL02a_FR.xml 11774337 u ∞ +0 1 +0 37.67/15.55
Transformed_CSR_04/Ex1_GL02a_GM.xml 11774591 u ∞ +0 1 +0 123.42/63.65
Transformed_CSR_04/Ex1_GL02a_L.xml 11774280 u ∞ +0 1 +0 20.21/8.06
Transformed_CSR_04/Ex1_GL02a_Z.xml 11774507 u ∞ +0 1 +0 627.14/296.12
Transformed_CSR_04/Ex1_GM03_C.xml 11774442 u timeout (wallclock)
Transformed_CSR_04/Ex1_GM03_FR.xml 11774376 u ∞ +0 1 +0 54.72/20.66
Transformed_CSR_04/Ex1_GM03_GM.xml 11774551 u ∞ +0 1 +0 568.58/296.06
Transformed_CSR_04/Ex1_GM03_L.xml 11774575 u ∞ +0 1 +0 0.01/0.01
Transformed_CSR_04/Ex1_GM03_Z.xml 11774185 u ∞ +0 1 +0 89.20/48.10
Transformed_CSR_04/Ex1_GM99_C.xml 11774234 u ∞ +0 1 +0 898.99/296.14
Transformed_CSR_04/Ex1_GM99_GM.xml 11774278 u ∞ +0 1 +0 12.93/6.01
Transformed_CSR_04/Ex1_GM99_L.xml 11774357 u ∞ +0 1 +0 21.58/8.11
Transformed_CSR_04/Ex1_Luc02b_C.xml 11774228 u ∞ +0 1 +0 664.20/296.84
Transformed_CSR_04/Ex1_Luc02b_FR.xml 11774327 u ∞ +0 1 +0 609.20/296.16
Transformed_CSR_04/Ex1_Luc02b_GM.xml 11774491 u ∞ +0 1 +0 36.50/16.82
Transformed_CSR_04/Ex1_Luc02b_L.xml 11774303 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/Ex1_Luc02b_Z.xml 11774481 u ∞ +0 1 +0 618.24/296.11
Transformed_CSR_04/Ex1_Luc04b_C.xml 11774365 s n1 +1 1 +0 2.30/0.68
Transformed_CSR_04/Ex1_Luc04b_FR.xml 11774426 u ∞ +0 1 +0 915.66/296.13
Transformed_CSR_04/Ex1_Luc04b_GM.xml 11774197 u ∞ +0 1 +0 987.64/296.28
Transformed_CSR_04/Ex1_Luc04b_L.xml 11774244 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/Ex1_Luc04b_Z.xml 11774525 u ∞ +0 1 +0 63.22/35.05
Transformed_CSR_04/Ex1_Zan97_C.xml 11774383 s n1 +1 1 +0 0.08/0.07
Transformed_CSR_04/Ex1_Zan97_FR.xml 11774263 u ∞ +0 1 +0 602.67/296.12
Transformed_CSR_04/Ex1_Zan97_GM.xml 11774458 s n1 +1 1 +0 0.17/0.07
Transformed_CSR_04/Ex1_Zan97_L.xml 11774521 u ∞ +0 1 +0 20.14/8.06
Transformed_CSR_04/Ex23_Luc06_C.xml 11774561 s n1 +1 1 +0 0.07/0.08
Transformed_CSR_04/Ex23_Luc06_FR.xml 11774515 s n1 +1 1 +0 0.09/0.06
Transformed_CSR_04/Ex23_Luc06_GM.xml 11774304 s n1 +1 1 +0 0.04/0.03
Transformed_CSR_04/Ex23_Luc06_Z.xml 11774297 s n1 +1 1 +0 0.04/0.03
Transformed_CSR_04/Ex24_GM04_C.xml 11774573 u ∞ +0 1 +0 0.12/0.10
Transformed_CSR_04/Ex24_GM04_FR.xml 11774251 u ∞ +0 1 +0 0.02/0.04
Transformed_CSR_04/Ex24_GM04_GM.xml 11774474 u ∞ +0 1 +0 0.11/0.06
Transformed_CSR_04/Ex24_GM04_L.xml 11774441 u ∞ +0 1 +0 19.89/8.06
Transformed_CSR_04/Ex24_GM04_Z.xml 11774310 u ∞ +0 1 +0 0.02/0.03
Transformed_CSR_04/Ex24_Luc06_C.xml 11774301 u ∞ +0 1 +0 1020.69/296.12
Transformed_CSR_04/Ex24_Luc06_GM.xml 11774356 u ∞ +0 1 +0 92.43/37.37
Transformed_CSR_04/Ex24_Luc06_L.xml 11774225 u ∞ +0 1 +0 18.58/8.06
Transformed_CSR_04/Ex25_Luc06_C.xml 11774412 s n1 +1 1 +0 0.06/0.04
Transformed_CSR_04/Ex25_Luc06_FR.xml 11774550 s n1 +1 1 +0 0.15/0.06
Transformed_CSR_04/Ex25_Luc06_GM.xml 11774378 s n1 +1 1 +0 0.12/0.06
Transformed_CSR_04/Ex25_Luc06_Z.xml 11774271 s n1 +1 1 +0 0.10/0.05
Transformed_CSR_04/Ex26_Luc03b_C.xml 11774430 u ∞ +0 1 +0 838.32/296.49
Transformed_CSR_04/Ex26_Luc03b_FR.xml 11774479 u ∞ +0 1 +0 215.20/112.75
Transformed_CSR_04/Ex26_Luc03b_GM.xml 11774247 u ∞ +0 1 +0 46.51/18.12
Transformed_CSR_04/Ex26_Luc03b_L.xml 11774513 s n1 +1 1 +0 0.10/0.05
Transformed_CSR_04/Ex26_Luc03b_Z.xml 11774277 u ∞ +0 1 +0 103.46/39.18
Transformed_CSR_04/Ex2_Luc02a_C.xml 11774352 u ∞ +0 1 +0 839.02/296.48
Transformed_CSR_04/Ex2_Luc02a_FR.xml 11774237 u ∞ +0 1 +0 58.33/27.91
Transformed_CSR_04/Ex2_Luc02a_GM.xml 11774488 u ∞ +0 1 +0 67.52/34.40
Transformed_CSR_04/Ex2_Luc02a_L.xml 11774279 u ∞ +0 1 +0 73.14/21.97
Transformed_CSR_04/Ex2_Luc02a_Z.xml 11774508 u ∞ +0 1 +0 79.10/22.27
Transformed_CSR_04/Ex2_Luc03b_C.xml 11774522 u ∞ +0 1 +0 828.81/296.53
Transformed_CSR_04/Ex2_Luc03b_FR.xml 11774480 u ∞ +0 1 +0 116.27/57.62
Transformed_CSR_04/Ex2_Luc03b_GM.xml 11774250 u ∞ +0 1 +0 37.81/17.43
Transformed_CSR_04/Ex2_Luc03b_L.xml 11774384 s n1 +1 1 +0 0.06/0.04
Transformed_CSR_04/Ex2_Luc03b_Z.xml 11774369 s n1 +1 1 +0 1.77/0.60
Transformed_CSR_04/Ex3_12_Luc96a_C.xml 11774528 u ∞ +0 1 +0 815.98/296.45
Transformed_CSR_04/Ex3_12_Luc96a_FR.xml 11774509 u ∞ +0 1 +0 376.74/275.33
Transformed_CSR_04/Ex3_12_Luc96a_GM.xml 11774314 u ∞ +0 1 +0 54.35/23.80
Transformed_CSR_04/Ex3_12_Luc96a_L.xml 11774389 u ∞ +0 1 +0 0.01/0.04
Transformed_CSR_04/Ex3_12_Luc96a_Z.xml 11774362 u ∞ +0 1 +0 389.85/296.03
Transformed_CSR_04/Ex3_2_Luc97_C.xml 11774577 u ∞ +0 1 +0 790.35/296.42
Transformed_CSR_04/Ex3_2_Luc97_FR.xml 11774452 u ∞ +0 1 +0 71.25/28.54
Transformed_CSR_04/Ex3_2_Luc97_GM.xml 11774267 u ∞ +0 1 +0 126.84/67.12
Transformed_CSR_04/Ex3_2_Luc97_L.xml 11774443 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/Ex3_2_Luc97_Z.xml 11774309 u ∞ +0 1 +0 46.66/18.23
Transformed_CSR_04/Ex3_3_25_Bor03_C.xml 11774429 u timeout (wallclock)
Transformed_CSR_04/Ex3_3_25_Bor03_FR.xml 11774386 u ∞ +0 1 +0 105.70/52.25
Transformed_CSR_04/Ex3_3_25_Bor03_GM.xml 11774230 u ∞ +0 1 +0 39.01/16.26
Transformed_CSR_04/Ex3_3_25_Bor03_L.xml 11774511 s n1 +1 1 +0 0.04/0.03
Transformed_CSR_04/Ex3_3_25_Bor03_Z.xml 11774276 u ∞ +0 1 +0 49.85/32.58
Transformed_CSR_04/Ex49_GM04_C.xml 11774293 u timeout (wallclock)
Transformed_CSR_04/Ex49_GM04_FR.xml 11774241 u ∞ +0 1 +0 124.04/77.60
Transformed_CSR_04/Ex49_GM04_GM.xml 11774487 u ∞ +0 1 +0 47.92/22.76
Transformed_CSR_04/Ex49_GM04_L.xml 11774220 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/Ex49_GM04_Z.xml 11774571 u ∞ +0 1 +0 14.81/4.13
Transformed_CSR_04/Ex4_4_Luc96b_C.xml 11774463 u ∞ +0 1 +0 414.16/164.43
Transformed_CSR_04/Ex4_4_Luc96b_FR.xml 11774432 u ∞ +0 1 +0 23.48/8.41
Transformed_CSR_04/Ex4_4_Luc96b_GM.xml 11774181 u ∞ +0 1 +0 88.41/42.70
Transformed_CSR_04/Ex4_4_Luc96b_L.xml 11774552 s n1 +1 1 +0 0.03/0.03
Transformed_CSR_04/Ex4_4_Luc96b_Z.xml 11774214 u ∞ +0 1 +0 24.56/9.63
Transformed_CSR_04/Ex4_7_15_Bor03_C.xml 11774289 s n1 +1 1 +0 0.13/0.06
Transformed_CSR_04/Ex4_7_15_Bor03_FR.xml 11774500 s n1 +1 1 +0 0.20/0.12
Transformed_CSR_04/Ex4_7_15_Bor03_GM.xml 11774324 s n1 +1 1 +0 0.18/0.11
Transformed_CSR_04/Ex4_7_15_Bor03_L.xml 11774212 s n1 +1 1 +0 0.03/0.03
Transformed_CSR_04/Ex4_7_15_Bor03_Z.xml 11774549 s n1 +1 1 +0 0.05/0.04
Transformed_CSR_04/Ex4_7_37_Bor03_C.xml 11774364 u timeout (wallclock)
Transformed_CSR_04/Ex4_7_37_Bor03_FR.xml 11774460 u ∞ +0 1 +0 770.56/296.12
Transformed_CSR_04/Ex4_7_37_Bor03_GM.xml 11774264 u ∞ +0 1 +0 573.71/296.14
Transformed_CSR_04/Ex4_7_37_Bor03_L.xml 11774243 u ∞ +0 1 +0 0.01/0.03
Transformed_CSR_04/Ex4_7_37_Bor03_Z.xml 11774523 u ∞ +0 1 +0 54.92/26.42
Transformed_CSR_04/Ex4_7_56_Bor03_C.xml 11774391 u timeout (wallclock)
Transformed_CSR_04/Ex4_7_56_Bor03_FR.xml 11774268 u ∞ +0 1 +0 295.10/115.39
Transformed_CSR_04/Ex4_7_56_Bor03_GM.xml 11774447 u ∞ +0 1 +0 71.95/35.29
Transformed_CSR_04/Ex4_7_56_Bor03_L.xml 11774531 u ∞ +0 1 +0 0.00/0.02
Transformed_CSR_04/Ex4_7_56_Bor03_Z.xml 11774239 u ∞ +0 1 +0 606.33/296.12
Transformed_CSR_04/Ex4_7_77_Bor03_C.xml 11774284 s n1 +1 1 +0 0.36/0.15
Transformed_CSR_04/Ex4_7_77_Bor03_FR.xml 11774294 s n1 +1 1 +0 0.05/0.04
Transformed_CSR_04/Ex4_7_77_Bor03_GM.xml 11774535 s n1 +1 1 +0 0.12/0.05
Transformed_CSR_04/Ex4_7_77_Bor03_L.xml 11774208 u ∞ +0 1 +0 0.00/0.02
Transformed_CSR_04/Ex4_DLMMU04_C.xml 11774256 u timeout (wallclock)
Transformed_CSR_04/Ex4_DLMMU04_FR.xml 11774418 u ∞ +0 1 +0 925.00/296.12
Transformed_CSR_04/Ex4_DLMMU04_GM.xml 11774199 u timeout (wallclock)
Transformed_CSR_04/Ex4_DLMMU04_L.xml 11774377 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/Ex4_DLMMU04_Z.xml 11774405 u ∞ +0 1 +0 937.03/296.13
Transformed_CSR_04/Ex4_Zan97_C.xml 11774202 u ∞ +0 1 +0 819.17/296.39
Transformed_CSR_04/Ex4_Zan97_FR.xml 11774192 u ∞ +0 1 +0 267.76/168.84
Transformed_CSR_04/Ex4_Zan97_GM.xml 11774425 u ∞ +0 1 +0 30.56/15.10
Transformed_CSR_04/Ex4_Zan97_L.xml 11774328 u ∞ +0 1 +0 0.01/0.07
Transformed_CSR_04/Ex4_Zan97_Z.xml 11774446 u ∞ +0 1 +0 889.73/296.14
Transformed_CSR_04/Ex5_7_Luc97_C.xml 11774567 u timeout (wallclock)
Transformed_CSR_04/Ex5_7_Luc97_FR.xml 11774334 u ∞ +0 1 +0 47.28/22.01
Transformed_CSR_04/Ex5_7_Luc97_GM.xml 11774593 u ∞ +0 1 +0 68.44/34.95
Transformed_CSR_04/Ex5_7_Luc97_L.xml 11774484 u ∞ +0 1 +0 0.01/0.03
Transformed_CSR_04/Ex5_7_Luc97_Z.xml 11774295 u ∞ +0 1 +0 42.38/19.13
Transformed_CSR_04/Ex5_DLMMU04_C.xml 11774541 u timeout (wallclock)
Transformed_CSR_04/Ex5_DLMMU04_FR.xml 11774358 u ∞ +0 1 +0 182.17/87.08
Transformed_CSR_04/Ex5_DLMMU04_GM.xml 11774566 u ∞ +0 1 +0 136.98/70.35
Transformed_CSR_04/Ex5_DLMMU04_L.xml 11774406 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/Ex5_DLMMU04_Z.xml 11774372 u ∞ +0 1 +0 102.45/44.63
Transformed_CSR_04/Ex5_Zan97_C.xml 11774526 s n1 +1 1 +0 2.30/0.64
Transformed_CSR_04/Ex5_Zan97_FR.xml 11774189 s n1 +1 1 +0 0.25/0.09
Transformed_CSR_04/Ex5_Zan97_GM.xml 11774428 u ∞ +0 1 +0 311.22/116.43
Transformed_CSR_04/Ex5_Zan97_L.xml 11774387 u ∞ +0 1 +0 0.01/0.06
Transformed_CSR_04/Ex5_Zan97_Z.xml 11774367 s n1 +1 1 +0 0.26/0.14
Transformed_CSR_04/Ex6_15_AEL02_C.xml 11774496 u timeout (wallclock)
Transformed_CSR_04/Ex6_15_AEL02_FR.xml 11774393 u ∞ +0 1 +0 172.24/83.10
Transformed_CSR_04/Ex6_15_AEL02_GM.xml 11774221 u ∞ +0 1 +0 888.11/297.28
Transformed_CSR_04/Ex6_15_AEL02_L.xml 11774423 u ∞ +0 1 +0 0.01/0.04
Transformed_CSR_04/Ex6_15_AEL02_Z.xml 11774336 u ∞ +0 1 +0 122.46/54.25
Transformed_CSR_04/Ex6_9_Luc02c_C.xml 11774473 u timeout (wallclock)
Transformed_CSR_04/Ex6_9_Luc02c_FR.xml 11774254 u ∞ +0 1 +0 604.21/296.12
Transformed_CSR_04/Ex6_9_Luc02c_GM.xml 11774471 u ∞ +0 1 +0 149.50/79.53
Transformed_CSR_04/Ex6_9_Luc02c_L.xml 11774559 u ∞ +0 1 +0 0.00/0.05
Transformed_CSR_04/Ex6_9_Luc02c_Z.xml 11774229 s n2 +1 1 +0 12.46/3.65
Transformed_CSR_04/Ex6_GM04_C.xml 11774375 s n1 +1 1 +0 0.18/0.07
Transformed_CSR_04/Ex6_GM04_FR.xml 11774344 u ∞ +0 1 +0 822.59/296.12
Transformed_CSR_04/Ex6_GM04_GM.xml 11774579 s n1 +1 1 +0 0.06/0.04
Transformed_CSR_04/Ex6_Luc98_C.xml 11774201 u ∞ +0 1 +0 830.27/297.64
Transformed_CSR_04/Ex6_Luc98_FR.xml 11774218 u ∞ +0 1 +0 109.48/59.02
Transformed_CSR_04/Ex6_Luc98_GM.xml 11774392 u ∞ +0 1 +0 375.63/222.90
Transformed_CSR_04/Ex6_Luc98_L.xml 11774326 s n1 +1 1 +0 0.02/0.08
Transformed_CSR_04/Ex6_Luc98_Z.xml 11774448 s n1 +1 1 +0 0.77/0.26
Transformed_CSR_04/Ex7_BLR02_C.xml 11774527 u timeout (wallclock)
Transformed_CSR_04/Ex7_BLR02_FR.xml 11774360 u ∞ +0 1 +0 611.40/296.12
Transformed_CSR_04/Ex7_BLR02_GM.xml 11774570 u ∞ +0 1 +0 39.96/16.47
Transformed_CSR_04/Ex7_BLR02_L.xml 11774388 u ∞ +0 1 +0 0.01/0.05
Transformed_CSR_04/Ex7_BLR02_Z.xml 11774359 u ∞ +0 1 +0 625.16/296.12
Transformed_CSR_04/Ex8_BLR02_C.xml 11774529 u ∞ +0 1 +0 815.40/296.46
Transformed_CSR_04/Ex8_BLR02_FR.xml 11774281 u ∞ +0 1 +0 614.49/296.12
Transformed_CSR_04/Ex8_BLR02_GM.xml 11774435 u ∞ +0 1 +0 36.61/14.61
Transformed_CSR_04/Ex8_BLR02_L.xml 11774390 u ∞ +0 1 +0 0.00/0.07
Transformed_CSR_04/Ex8_BLR02_Z.xml 11774363 u ∞ +0 1 +0 605.49/296.13
Transformed_CSR_04/Ex9_BLR02_C.xml 11774194 u timeout (wallclock)
Transformed_CSR_04/Ex9_BLR02_FR.xml 11774260 u ∞ +0 1 +0 75.74/34.01
Transformed_CSR_04/Ex9_BLR02_GM.xml 11774451 u ∞ +0 1 +0 37.12/14.47
Transformed_CSR_04/Ex9_BLR02_L.xml 11774319 s n1 +1 1 +0 0.04/0.04
Transformed_CSR_04/Ex9_BLR02_Z.xml 11774455 u ∞ +0 1 +0 162.25/90.14
Transformed_CSR_04/Ex9_Luc04_C.xml 11774290 u ∞ +0 1 +0 479.98/237.29
Transformed_CSR_04/Ex9_Luc04_GM.xml 11774371 u ∞ +0 1 +0 15.23/6.82
Transformed_CSR_04/Ex9_Luc04_L.xml 11774213 u ∞ +0 1 +0 3.24/1.72
Transformed_CSR_04/Ex9_Luc06_C.xml 11774186 u ∞ +0 1 +0 0.05/0.04
Transformed_CSR_04/Ex9_Luc06_FR.xml 11774493 u ∞ +0 1 +0 0.09/0.04
Transformed_CSR_04/Ex9_Luc06_GM.xml 11774329 u ∞ +0 1 +0 0.05/0.07
Transformed_CSR_04/ExAppendixB_AEL03_C.xml 11774424 u ∞ +0 1 +0 911.02/296.13
Transformed_CSR_04/ExAppendixB_AEL03_FR.xml 11774312 u ∞ +0 1 +0 41.62/17.40
Transformed_CSR_04/ExAppendixB_AEL03_GM.xml 11774503 u ∞ +0 1 +0 972.77/296.24
Transformed_CSR_04/ExAppendixB_AEL03_L.xml 11774497 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/ExAppendixB_AEL03_Z.xml 11774266 u ∞ +0 1 +0 33.92/14.33
Transformed_CSR_04/ExConc_Zan97_C.xml 11774397 s n1 +1 1 +0 0.07/0.05
Transformed_CSR_04/ExConc_Zan97_FR.xml 11774269 s n1 +1 1 +0 0.05/0.03
Transformed_CSR_04/ExConc_Zan97_GM.xml 11774449 s n1 +1 1 +0 0.04/0.03
Transformed_CSR_04/ExConc_Zan97_Z.xml 11774236 u ∞ +0 1 +0 21.21/8.06
Transformed_CSR_04/ExIntrod_GM01_C.xml 11774490 s n1 +1 1 +0 4.15/1.09
Transformed_CSR_04/ExIntrod_GM01_FR.xml 11774331 u ∞ +0 1 +0 771.35/296.22
Transformed_CSR_04/ExIntrod_GM01_GM.xml 11774590 u ∞ +0 1 +0 1053.85/296.35
Transformed_CSR_04/ExIntrod_GM01_L.xml 11774410 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/ExIntrod_GM01_Z.xml 11774339 u ∞ +0 1 +0 967.27/296.27
Transformed_CSR_04/ExIntrod_GM04_C.xml 11774348 s n1 +1 1 +0 1.28/0.42
Transformed_CSR_04/ExIntrod_GM04_FR.xml 11774576 u ∞ +0 1 +0 317.98/122.98
Transformed_CSR_04/ExIntrod_GM04_GM.xml 11774346 s n3 +1 1 +0 130.98/34.57
Transformed_CSR_04/ExIntrod_GM04_L.xml 11774275 u ∞ +0 1 +0 0.00/0.02
Transformed_CSR_04/ExIntrod_GM04_Z.xml 11774519 u ∞ +0 1 +0 818.07/296.12
Transformed_CSR_04/ExIntrod_GM99_C.xml 11774183 u timeout (wallclock)
Transformed_CSR_04/ExIntrod_GM99_FR.xml 11774431 u ∞ +0 1 +0 87.13/50.39
Transformed_CSR_04/ExIntrod_GM99_GM.xml 11774182 u ∞ +0 1 +0 86.88/49.11
Transformed_CSR_04/ExIntrod_GM99_L.xml 11774305 u ∞ +0 1 +0 0.00/0.02
Transformed_CSR_04/ExIntrod_GM99_Z.xml 11774445 u ∞ +0 1 +0 66.22/39.03
Transformed_CSR_04/ExIntrod_Zan97_C.xml 11774478 u ∞ +0 1 +0 952.19/296.12
Transformed_CSR_04/ExIntrod_Zan97_FR.xml 11774307 u ∞ +0 1 +0 39.66/17.57
Transformed_CSR_04/ExIntrod_Zan97_GM.xml 11774518 u ∞ +0 1 +0 587.79/296.15
Transformed_CSR_04/ExIntrod_Zan97_L.xml 11774565 u ∞ +0 1 +0 0.01/0.06
Transformed_CSR_04/ExIntrod_Zan97_Z.xml 11774227 u ∞ +0 1 +0 40.32/18.33
Transformed_CSR_04/ExProp7_Luc06_C.xml 11774272 s n1 +1 1 +0 0.10/0.05
Transformed_CSR_04/ExProp7_Luc06_FR.xml 11774338 s n1 +1 1 +0 0.06/0.04
Transformed_CSR_04/ExProp7_Luc06_GM.xml 11774584 u ∞ +0 1 +0 1168.52/296.07
Transformed_CSR_04/ExProp7_Luc06_L.xml 11774342 s n1 +1 1 +0 0.09/0.05
Transformed_CSR_04/ExProp7_Luc06_Z.xml 11774414 s n1 +1 1 +0 0.06/0.04
Transformed_CSR_04/ExSec11_1_Luc02a_C.xml 11774402 u ∞ +0 1 +0 800.31/296.39
Transformed_CSR_04/ExSec11_1_Luc02a_FR.xml 11774404 u ∞ +0 1 +0 62.42/28.30
Transformed_CSR_04/ExSec11_1_Luc02a_GM.xml 11774215 u ∞ +0 1 +0 75.14/38.63
Transformed_CSR_04/ExSec11_1_Luc02a_L.xml 11774538 u ∞ +0 1 +0 81.34/22.55
Transformed_CSR_04/ExSec11_1_Luc02a_Z.xml 11774259 u ∞ +0 1 +0 81.88/23.81
Transformed_CSR_04/ExSec4_2_DLMMU04_C.xml 11774409 u timeout (wallclock)
Transformed_CSR_04/ExSec4_2_DLMMU04_FR.xml 11774306 u ∞ +0 1 +0 382.30/205.86
Transformed_CSR_04/ExSec4_2_DLMMU04_GM.xml 11774512 u ∞ +0 1 +0 700.72/300.72
Transformed_CSR_04/ExSec4_2_DLMMU04_L.xml 11774547 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/ExSec4_2_DLMMU04_Z.xml 11774253 u ∞ +0 1 +0 658.28/296.13
Transformed_CSR_04/LengthOfFiniteLists_complete-noand_FR.xml 11774502 u ∞ +0 1 +0 496.95/296.13
Transformed_CSR_04/LengthOfFiniteLists_complete-noand_L.xml 11774580 u ∞ +0 1 +0 0.03/0.02
Transformed_CSR_04/LengthOfFiniteLists_complete-noand_Z.xml 11774187 u ∞ +0 1 +0 487.32/296.06
Transformed_CSR_04/LengthOfFiniteLists_complete_C.xml 11774332 u timeout (wallclock)
Transformed_CSR_04/LengthOfFiniteLists_complete_FR.xml 11774195 u timeout (wallclock)
Transformed_CSR_04/LengthOfFiniteLists_complete_GM.xml 11774419 u timeout (wallclock)
Transformed_CSR_04/LengthOfFiniteLists_complete_L.xml 11774261 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/LengthOfFiniteLists_complete_noand_C.xml 11774578 u ∞ +0 1 +0 1021.70/296.07
Transformed_CSR_04/LengthOfFiniteLists_complete_noand_GM.xml 11774524 u timeout (wallclock)
Transformed_CSR_04/LengthOfFiniteLists_complete_Z.xml 11774501 u timeout (wallclock)
Transformed_CSR_04/LengthOfFiniteLists_nokinds-noand_FR.xml 11774427 u ∞ +0 1 +0 136.70/73.61
Transformed_CSR_04/LengthOfFiniteLists_nokinds-noand_L.xml 11774381 u ∞ +0 1 +0 0.01/0.05
Transformed_CSR_04/LengthOfFiniteLists_nokinds-noand_Z.xml 11774398 u ∞ +0 1 +0 128.76/69.93
Transformed_CSR_04/LengthOfFiniteLists_nokinds_C.xml 11774325 u timeout (wallclock)
Transformed_CSR_04/LengthOfFiniteLists_nokinds_FR.xml 11774313 u timeout (wallclock)
Transformed_CSR_04/LengthOfFiniteLists_nokinds_GM.xml 11774510 u ∞ +0 1 +0 106.31/50.06
Transformed_CSR_04/LengthOfFiniteLists_nokinds_L.xml 11774200 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/LengthOfFiniteLists_nokinds_noand_C.xml 11774380 u ∞ +0 1 +0 898.43/296.18
Transformed_CSR_04/LengthOfFiniteLists_nokinds_noand_GM.xml 11774385 u ∞ +0 1 +0 863.47/296.35
Transformed_CSR_04/LengthOfFiniteLists_nokinds_Z.xml 11774588 u timeout (wallclock)
Transformed_CSR_04/LengthOfFiniteLists_nosorts-noand_FR.xml 11774589 u ∞ +0 1 +0 791.21/296.11
Transformed_CSR_04/LengthOfFiniteLists_nosorts-noand_L.xml 11774504 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/LengthOfFiniteLists_nosorts_C.xml 11774316 s n1 +1 1 +0 0.43/0.17
Transformed_CSR_04/LengthOfFiniteLists_nosorts_FR.xml 11774415 u ∞ +0 1 +0 601.93/296.07
Transformed_CSR_04/LengthOfFiniteLists_nosorts_GM.xml 11774198 u ∞ +0 1 +0 972.62/296.14
Transformed_CSR_04/LengthOfFiniteLists_nosorts_L.xml 11774190 u ∞ +0 1 +0 0.01/0.03
Transformed_CSR_04/LengthOfFiniteLists_nosorts_noand_C.xml 11774505 s n1 +1 1 +0 1.43/0.41
Transformed_CSR_04/LengthOfFiniteLists_nosorts_noand_GM.xml 11774558 u ∞ +0 1 +0 1054.75/296.18
Transformed_CSR_04/LISTUTILITIES_complete-noand_FR.xml 11774403 u ∞ +0 1 +0 1058.93/296.24
Transformed_CSR_04/LISTUTILITIES_complete-noand_L.xml 11774456 u ∞ +0 1 +0 0.04/0.03
Transformed_CSR_04/LISTUTILITIES_complete-noand_Z.xml 11774320 u ∞ +0 1 +0 1056.11/296.24
Transformed_CSR_04/LISTUTILITIES_complete_C.xml 11774542 u ∞ +0 1 +0 1102.33/296.80
Transformed_CSR_04/LISTUTILITIES_complete_FR.xml 11774379 u ∞ +0 1 +0 426.88/296.17
Transformed_CSR_04/LISTUTILITIES_complete_GM.xml 11774555 u timeout (wallclock)
Transformed_CSR_04/LISTUTILITIES_complete_L.xml 11774407 u ∞ +0 1 +0 0.03/0.02
Transformed_CSR_04/LISTUTILITIES_complete_noand_C.xml 11774454 u timeout (wallclock)
Transformed_CSR_04/LISTUTILITIES_complete_noand_GM.xml 11774411 u timeout (wallclock)
Transformed_CSR_04/LISTUTILITIES_complete_Z.xml 11774373 u ∞ +0 1 +0 792.20/296.09
Transformed_CSR_04/LISTUTILITIES_nokinds-noand_FR.xml 11774492 u ∞ +0 1 +0 847.99/296.18
Transformed_CSR_04/LISTUTILITIES_nokinds-noand_L.xml 11774416 u ∞ +0 1 +0 0.03/0.02
Transformed_CSR_04/LISTUTILITIES_nokinds-noand_Z.xml 11774343 u ∞ +0 1 +0 847.87/296.19
Transformed_CSR_04/LISTUTILITIES_nokinds_C.xml 11774298 u timeout (wallclock)
Transformed_CSR_04/LISTUTILITIES_nokinds_FR.xml 11774562 u timeout (wallclock)
Transformed_CSR_04/LISTUTILITIES_nokinds_GM.xml 11774370 u timeout (wallclock)
Transformed_CSR_04/LISTUTILITIES_nokinds_L.xml 11774224 u ∞ +0 1 +0 0.01/0.01
Transformed_CSR_04/LISTUTILITIES_nokinds_noand_C.xml 11774417 u timeout (wallclock)
Transformed_CSR_04/LISTUTILITIES_nokinds_noand_GM.xml 11774539 u timeout (wallclock)
Transformed_CSR_04/LISTUTILITIES_nokinds_Z.xml 11774564 u timeout (wallclock)
Transformed_CSR_04/LISTUTILITIES_nosorts-noand_FR.xml 11774444 u ∞ +0 1 +0 681.12/296.13
Transformed_CSR_04/LISTUTILITIES_nosorts-noand_L.xml 11774249 u ∞ +0 1 +0 0.01/0.04
Transformed_CSR_04/LISTUTILITIES_nosorts-noand_Z.xml 11774520 u ∞ +0 1 +0 687.30/296.12
Transformed_CSR_04/LISTUTILITIES_nosorts_C.xml 11774288 u ∞ +0 1 +0 785.79/296.42
Transformed_CSR_04/LISTUTILITIES_nosorts_FR.xml 11774255 u ∞ +0 1 +0 576.93/296.14
Transformed_CSR_04/LISTUTILITIES_nosorts_GM.xml 11774461 u ∞ +0 1 +0 675.74/296.75
Transformed_CSR_04/LISTUTILITIES_nosorts_L.xml 11774211 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/LISTUTILITIES_nosorts_noand_C.xml 11774248 u ∞ +0 1 +0 820.05/296.33
Transformed_CSR_04/LISTUTILITIES_nosorts_noand_GM.xml 11774485 u timeout (wallclock)
Transformed_CSR_04/LISTUTILITIES_nosorts_Z.xml 11774548 u ∞ +0 1 +0 572.65/296.13
Transformed_CSR_04/MYNAT_complete-noand_FR.xml 11774292 u ∞ +0 1 +0 710.98/296.13
Transformed_CSR_04/MYNAT_complete-noand_L.xml 11774341 u ∞ +0 1 +0 0.03/0.02
Transformed_CSR_04/MYNAT_complete-noand_Z.xml 11774413 u ∞ +0 1 +0 707.57/296.13
Transformed_CSR_04/MYNAT_complete_C.xml 11774299 u timeout (wallclock)
Transformed_CSR_04/MYNAT_complete_FR.xml 11774483 u timeout (wallclock)
Transformed_CSR_04/MYNAT_complete_GM.xml 11774232 u timeout (wallclock)
Transformed_CSR_04/MYNAT_complete_L.xml 11774223 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/MYNAT_complete_noand_C.xml 11774340 u ∞ +0 1 +0 1030.89/296.20
Transformed_CSR_04/MYNAT_complete_noand_GM.xml 11774308 u timeout (wallclock)
Transformed_CSR_04/MYNAT_complete_Z.xml 11774563 u timeout (wallclock)
Transformed_CSR_04/MYNAT_nokinds-noand_FR.xml 11774196 u ∞ +0 1 +0 666.33/296.13
Transformed_CSR_04/MYNAT_nokinds-noand_L.xml 11774302 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/MYNAT_nokinds-noand_Z.xml 11774477 u ∞ +0 1 +0 663.91/296.13
Transformed_CSR_04/MYNAT_nokinds_C.xml 11774258 u ∞ +0 1 +0 736.50/296.06
Transformed_CSR_04/MYNAT_nokinds_FR.xml 11774374 u ∞ +0 1 +0 664.15/296.08
Transformed_CSR_04/MYNAT_nokinds_GM.xml 11774557 u ∞ +0 1 +0 681.02/296.15
Transformed_CSR_04/MYNAT_nokinds_L.xml 11774382 u ∞ +0 1 +0 0.01/0.03
Transformed_CSR_04/MYNAT_nokinds_noand_C.xml 11774300 u ∞ +0 1 +0 751.91/296.14
Transformed_CSR_04/MYNAT_nokinds_noand_GM.xml 11774205 u timeout (wallclock)
Transformed_CSR_04/MYNAT_nokinds_Z.xml 11774400 u ∞ +0 1 +0 672.93/296.14
Transformed_CSR_04/MYNAT_nosorts-noand_FR.xml 11774354 u ∞ +0 1 +0 1159.64/296.10
Transformed_CSR_04/MYNAT_nosorts-noand_L.xml 11774586 u ∞ +0 1 +0 0.01/0.01
Transformed_CSR_04/MYNAT_nosorts_C.xml 11774246 u ∞ +0 1 +0 121.76/61.24
Transformed_CSR_04/MYNAT_nosorts_FR.xml 11774482 s n2 +1 1 +0 2.88/0.94
Transformed_CSR_04/MYNAT_nosorts_GM.xml 11774235 u ∞ +0 1 +0 577.84/296.05
Transformed_CSR_04/MYNAT_nosorts_L.xml 11774366 u ∞ +0 1 +0 0.01/0.06
Transformed_CSR_04/MYNAT_nosorts_noand_C.xml 11774587 u ∞ +0 1 +0 228.67/120.70
Transformed_CSR_04/MYNAT_nosorts_noand_GM.xml 11774368 u ∞ +0 1 +0 629.31/296.21
Transformed_CSR_04/OvConsOS_complete-noand_FR.xml 11774226 u ∞ +0 1 +0 669.57/296.14
Transformed_CSR_04/OvConsOS_complete-noand_L.xml 11774464 u ∞ +0 1 +0 0.03/0.02
Transformed_CSR_04/OvConsOS_complete-noand_Z.xml 11774285 u ∞ +0 1 +0 666.35/296.10
Transformed_CSR_04/OvConsOS_complete_C.xml 11774462 u ∞ +0 1 +0 1064.40/296.17
Transformed_CSR_04/OvConsOS_complete_FR.xml 11774317 u timeout (wallclock)
Transformed_CSR_04/OvConsOS_complete_GM.xml 11774506 u timeout (wallclock)
Transformed_CSR_04/OvConsOS_complete_L.xml 11774553 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/OvConsOS_complete_noand_C.xml 11774468 u timeout (wallclock)
Transformed_CSR_04/OvConsOS_complete_noand_GM.xml 11774191 u timeout (wallclock)
Transformed_CSR_04/OvConsOS_complete_Z.xml 11774216 u timeout (wallclock)
Transformed_CSR_04/OvConsOS_nokinds-noand_FR.xml 11774546 u ∞ +0 1 +0 250.36/147.53
Transformed_CSR_04/OvConsOS_nokinds-noand_L.xml 11774422 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/OvConsOS_nokinds-noand_Z.xml 11774335 u ∞ +0 1 +0 241.40/146.10
Transformed_CSR_04/OvConsOS_nokinds_C.xml 11774486 u timeout (wallclock)
Transformed_CSR_04/OvConsOS_nokinds_FR.xml 11774395 u timeout (wallclock)
Transformed_CSR_04/OvConsOS_nokinds_GM.xml 11774222 u ∞ +0 1 +0 653.88/296.18
Transformed_CSR_04/OvConsOS_nokinds_L.xml 11774568 u ∞ +0 1 +0 0.01/0.07
Transformed_CSR_04/OvConsOS_nokinds_noand_C.xml 11774421 u ∞ +0 1 +0 833.42/299.33
Transformed_CSR_04/OvConsOS_nokinds_noand_GM.xml 11774498 u timeout (wallclock)
Transformed_CSR_04/OvConsOS_nokinds_Z.xml 11774217 u timeout (wallclock)
Transformed_CSR_04/OvConsOS_nosorts-noand_FR.xml 11774476 u ∞ +0 1 +0 180.11/67.42
Transformed_CSR_04/OvConsOS_nosorts-noand_L.xml 11774240 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/OvConsOS_nosorts-noand_Z.xml 11774530 u ∞ +0 1 +0 799.36/296.08
Transformed_CSR_04/OvConsOS_nosorts_C.xml 11774470 s n1 +1 1 +0 1.19/0.34
Transformed_CSR_04/OvConsOS_nosorts_FR.xml 11774282 u ∞ +0 1 +0 933.36/296.29
Transformed_CSR_04/OvConsOS_nosorts_GM.xml 11774540 u ∞ +0 1 +0 956.64/296.13
Transformed_CSR_04/OvConsOS_nosorts_L.xml 11774556 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/OvConsOS_nosorts_noand_C.xml 11774242 u timeout (wallclock)
Transformed_CSR_04/OvConsOS_nosorts_noand_GM.xml 11774436 u ∞ +0 1 +0 724.75/296.31
Transformed_CSR_04/OvConsOS_nosorts_Z.xml 11774206 u ∞ +0 1 +0 899.35/296.13
Transformed_CSR_04/PALINDROME_complete-noand_FR.xml 11774583 u ∞ +0 1 +0 0.19/0.14
Transformed_CSR_04/PALINDROME_complete-noand_L.xml 11774437 u ∞ +0 1 +0 1161.61/296.18
Transformed_CSR_04/PALINDROME_complete-noand_Z.xml 11774315 u ∞ +0 1 +0 0.29/0.17
Transformed_CSR_04/PALINDROME_complete_C.xml 11774330 u ∞ +0 1 +0 0.57/0.32
Transformed_CSR_04/PALINDROME_complete_FR.xml 11774532 u ∞ +0 1 +0 0.17/0.11
Transformed_CSR_04/PALINDROME_complete_GM.xml 11774296 u timeout (wallclock)
Transformed_CSR_04/PALINDROME_complete_L.xml 11774203 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/PALINDROME_complete_noand_C.xml 11774438 u ∞ +0 1 +0 1.08/0.58
Transformed_CSR_04/PALINDROME_complete_noand_GM.xml 11774554 u timeout (wallclock)
Transformed_CSR_04/PALINDROME_complete_Z.xml 11774585 u ∞ +0 1 +0 0.21/0.11
Transformed_CSR_04/PALINDROME_nokinds-noand_FR.xml 11774514 u ∞ +0 1 +0 0.11/0.11
Transformed_CSR_04/PALINDROME_nokinds-noand_L.xml 11774321 u ∞ +0 1 +0 557.00/296.10
Transformed_CSR_04/PALINDROME_nokinds-noand_Z.xml 11774459 u ∞ +0 1 +0 0.16/0.08
Transformed_CSR_04/PALINDROME_nokinds_C.xml 11774219 u ∞ +0 1 +0 0.14/0.08
Transformed_CSR_04/PALINDROME_nokinds_FR.xml 11774345 u ∞ +0 1 +0 0.14/0.11
Transformed_CSR_04/PALINDROME_nokinds_GM.xml 11774581 u ∞ +0 1 +0 0.15/0.07
Transformed_CSR_04/PALINDROME_nokinds_L.xml 11774291 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/PALINDROME_nokinds_noand_C.xml 11774322 u ∞ +0 1 +0 0.29/0.20
Transformed_CSR_04/PALINDROME_nokinds_noand_GM.xml 11774534 u ∞ +0 1 +0 0.16/0.10
Transformed_CSR_04/PALINDROME_nokinds_Z.xml 11774489 u ∞ +0 1 +0 0.11/0.07
Transformed_CSR_04/PALINDROME_nosorts_C.xml 11774207 u ∞ +0 1 +0 0.19/0.08
Transformed_CSR_04/PALINDROME_nosorts_GM.xml 11774262 u ∞ +0 1 +0 0.06/0.04
Transformed_CSR_04/PALINDROME_nosorts_L.xml 11774283 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/PALINDROME_nosorts_noand_C.xml 11774569 u ∞ +0 1 +0 0.11/0.06
Transformed_CSR_04/PALINDROME_nosorts_noand_GM.xml 11774466 u ∞ +0 1 +0 0.06/0.05
Transformed_CSR_04/PEANO_complete-noand_FR.xml 11774231 u ∞ +0 1 +0 651.06/296.13
Transformed_CSR_04/PEANO_complete-noand_L.xml 11774467 u ∞ +0 1 +0 0.01/0.01
Transformed_CSR_04/PEANO_complete-noand_Z.xml 11774286 u ∞ +0 1 +0 652.73/296.13
Transformed_CSR_04/PEANO_complete_C.xml 11774572 u timeout (wallclock)
Transformed_CSR_04/PEANO_complete_FR.xml 11774209 u timeout (wallclock)
Transformed_CSR_04/PEANO_complete_GM.xml 11774401 u timeout (wallclock)
Transformed_CSR_04/PEANO_complete_L.xml 11774440 u ∞ +0 1 +0 0.01/0.01
Transformed_CSR_04/PEANO_complete_noand_C.xml 11774465 u ∞ +0 1 +0 791.64/296.08
Transformed_CSR_04/PEANO_complete_noand_GM.xml 11774188 u timeout (wallclock)
Transformed_CSR_04/PEANO_complete_Z.xml 11774311 u timeout (wallclock)
Transformed_CSR_04/PEANO_nokinds-noand_FR.xml 11774545 u ∞ +0 1 +0 564.90/296.13
Transformed_CSR_04/PEANO_nokinds-noand_L.xml 11774544 u ∞ +0 1 +0 0.01/0.02
Transformed_CSR_04/PEANO_nokinds-noand_Z.xml 11774252 u ∞ +0 1 +0 566.63/296.07
Transformed_CSR_04/PEANO_nokinds_C.xml 11774433 u ∞ +0 1 +0 708.95/296.13
Transformed_CSR_04/PEANO_nokinds_FR.xml 11774495 u ∞ +0 1 +0 592.90/296.13
Transformed_CSR_04/PEANO_nokinds_GM.xml 11774318 u ∞ +0 1 +0 91.26/49.00
Transformed_CSR_04/PEANO_nokinds_L.xml 11774516 u ∞ +0 1 +0 0.00/0.04
Transformed_CSR_04/PEANO_nokinds_noand_C.xml 11774543 u ∞ +0 1 +0 693.80/296.05
Transformed_CSR_04/PEANO_nokinds_noand_GM.xml 11774499 u ∞ +0 1 +0 90.54/35.86
Transformed_CSR_04/PEANO_nokinds_Z.xml 11774273 u ∞ +0 1 +0 589.89/296.13
Transformed_CSR_04/PEANO_nosorts-noand_FR.xml 11774475 s n1 +1 1 +0 1.32/0.36
Transformed_CSR_04/PEANO_nosorts-noand_L.xml 11774349 u ∞ +0 1 +0 0.01/0.06
Transformed_CSR_04/PEANO_nosorts_C.xml 11774420 s n1 +1 1 +0 0.14/0.06
Transformed_CSR_04/PEANO_nosorts_FR.xml 11774184 s n1 +1 1 +0 0.09/0.05
Transformed_CSR_04/PEANO_nosorts_GM.xml 11774434 u ∞ +0 1 +0 90.22/32.77
Transformed_CSR_04/PEANO_nosorts_L.xml 11774494 u ∞ +0 1 +0 0.00/0.01
Transformed_CSR_04/PEANO_nosorts_noand_C.xml 11774350 s n1 +1 1 +0 0.99/0.35
Transformed_CSR_04/PEANO_nosorts_noand_GM.xml 11774439 u ∞ +0 1 +0 151.01/58.80
Strategy_removed_AG01/#4.14.xml 11774618 s n1 +1 1 +0 1.27/0.45
Strategy_removed_AG01/#4.16.xml 11774604 s n1 +1 1 +0 0.69/0.25
Strategy_removed_AG01/#4.17.xml 11774596 s n1 +1 1 +0 0.03/0.03
Strategy_removed_AG01/#4.19.xml 11774600 u ∞ +0 1 +0 0.04/0.03
Strategy_removed_AG01/#4.2.xml 11774611 s n1 +1 1 +0 1.78/0.71
Strategy_removed_AG01/#4.20a.xml 11774608 s n1 +1 1 +0 0.10/0.06
Strategy_removed_AG01/#4.22.xml 11774594 u ∞ +0 1 +0 12.91/5.56
Strategy_removed_AG01/#4.23.xml 11774605 u ∞ +0 1 +0 17.08/6.75
Strategy_removed_AG01/#4.25.xml 11774595 u ∞ +0 1 +0 0.02/0.03
Strategy_removed_AG01/#4.26.xml 11774617 u ∞ +0 1 +0 21.11/9.23
Strategy_removed_AG01/#4.27.xml 11774612 u timeout (wallclock)
Strategy_removed_AG01/#4.28.xml 11774616 s n1 +1 1 +0 8.07/2.33
Strategy_removed_AG01/#4.29.xml 11774613 u ∞ +0 1 +0 656.46/296.04
Strategy_removed_AG01/#4.30.xml 11774614 u ∞ +0 1 +0 25.39/8.30
Strategy_removed_AG01/#4.30a.xml 11774610 u ∞ +0 1 +0 18.88/6.87
Strategy_removed_AG01/#4.30b.xml 11774603 u ∞ +0 1 +0 25.87/8.52
Strategy_removed_AG01/#4.30c.xml 11774599 u ∞ +0 1 +0 28.26/9.69
Strategy_removed_AG01/#4.32.xml 11774606 s n2 +1 1 +0 0.93/0.52
Strategy_removed_AG01/#4.33.xml 11774602 u ∞ +0 1 +0 143.40/48.54
Strategy_removed_AG01/#4.34.xml 11774601 s n2 +1 1 +0 1.41/0.75
Strategy_removed_AG01/#4.35.xml 11774607 u ∞ +0 1 +0 0.16/0.07
Strategy_removed_AG01/#4.36.xml 11774609 u ∞ +0 1 +0 910.46/296.81
Strategy_removed_AG01/#4.37.xml 11774615 s n1 +1 1 +0 0.04/0.03
Strategy_removed_AG01/#4.37a.xml 11774597 s n1 +1 1 +0 0.03/0.03
Strategy_removed_AG01/#4.7.xml 11774598 u ∞ +0 1 +0 775.44/296.04
Beerendonk_07/1.xml 11774152 u ∞ +0 1 +0 15.31/5.63
Beerendonk_07/10.xml 11774148 u ∞ +0 1 +0 25.01/9.33
Beerendonk_07/11.xml 11774145 u ∞ +0 1 +0 20.86/7.51
Beerendonk_07/12.xml 11774163 u ∞ +0 1 +0 27.06/13.15
Beerendonk_07/13.xml 11774154 u ∞ +0 1 +0 21.83/7.76
Beerendonk_07/14.xml 11774155 u ∞ +0 1 +0 25.99/8.58
Beerendonk_07/15.xml 11774162 u ∞ +0 1 +0 751.62/296.12
Beerendonk_07/16.xml 11774146 u ∞ +0 1 +0 904.41/296.72
Beerendonk_07/17.xml 11774147 u ∞ +0 1 +0 758.47/296.14
Beerendonk_07/18.xml 11774144 u ∞ +0 1 +0 708.69/296.08
Beerendonk_07/19.xml 11774149 u timeout (wallclock)
Beerendonk_07/2.xml 11774157 u ∞ +0 1 +0 17.40/6.90
Beerendonk_07/20.xml 11774160 u ∞ +0 1 +0 692.03/296.03
Beerendonk_07/21.xml 11774156 u timeout (wallclock)
Beerendonk_07/22.xml 11774153 u ∞ +0 1 +0 18.98/6.67
Beerendonk_07/23.xml 11774140 u ∞ +0 1 +0 21.27/7.85
Beerendonk_07/24.xml 11774142 u ∞ +0 1 +0 670.32/296.13
Beerendonk_07/3.xml 11774161 u ∞ +0 1 +0 25.47/10.41
Beerendonk_07/4.xml 11774159 u ∞ +0 1 +0 12.03/4.57
Beerendonk_07/5.xml 11774158 u ∞ +0 1 +0 60.34/25.71
Beerendonk_07/6.xml 11774151 u ∞ +0 1 +0 13.93/5.73
Beerendonk_07/7.xml 11774141 u ∞ +0 1 +0 766.71/296.15
Beerendonk_07/8.xml 11774150 u ∞ +0 1 +0 639.02/296.10
Beerendonk_07/9.xml 11774143 u timeout (wallclock)
Mixed_TRS/Ex1_Luc04b_GM.xml 11774174 u ∞ +0 1 +0 984.17/296.13
Mixed_TRS/fossacs.xml 11774180 u ∞ +0 1 +0 72.81/29.16
Mixed_TRS/gcd.xml 11774164 u ∞ +0 1 +0 774.97/296.12
Mixed_TRS/gcdMinMax.xml 11774176 u ∞ +0 1 +0 893.79/296.04
Mixed_TRS/gcd_triple.xml 11774166 u ∞ +0 1 +0 847.88/299.93
Mixed_TRS/hydra-Zantema06.xml 11774173 u timeout (wallclock)
Mixed_TRS/hydra.xml 11774169 s n2 +1 1 +0 12.21/3.17
Mixed_TRS/jones1.xml 11774179 s n1 +1 1 +0 0.08/0.04
Mixed_TRS/jones2.xml 11774168 s n2 +1 1 +0 5.88/1.66
Mixed_TRS/jones4.xml 11774172 s n1 +1 1 +0 0.05/0.07
Mixed_TRS/jones5.xml 11774170 u ∞ +0 1 +0 8.90/3.50
Mixed_TRS/jones6.xml 11774178 s n1 +1 1 +0 0.06/0.05
Mixed_TRS/minsort.xml 11774177 u ∞ +0 1 +0 662.08/296.03
Mixed_TRS/perfect.xml 11774165 u ∞ +0 1 +0 23.95/8.05
Mixed_TRS/perfect2.xml 11774167 u timeout (wallclock)
Mixed_TRS/test1.xml 11774171 u ∞ +0 1 +0 7.75/3.83
Mixed_TRS/while.xml 11774175 u ∞ +0 1 +0 11.83/4.49
AProVE_06/div_notCeTermin.xml 11774111 u ∞ +0 1 +0 38.49/17.17
AProVE_06/div_notTermin.xml 11774106 u ∞ +0 1 +0 39.30/18.48
AProVE_06/factorial1.xml 11774113 u ∞ +0 1 +0 293.38/189.40
AProVE_06/factorial2.xml 11774107 u ∞ +0 1 +0 32.00/12.10
AProVE_06/identity.xml 11774116 u ∞ +0 1 +0 612.77/296.14
AProVE_06/logarithm.xml 11774114 u ∞ +0 1 +0 30.60/12.61
AProVE_06/modulo.xml 11774112 u ∞ +0 1 +0 0.05/0.04
AProVE_06/nonterm.xml 11774110 u ∞ +0 1 +0 0.11/0.05
AProVE_06/quicksort.xml 11774115 u ∞ +0 1 +0 178.40/105.55
AProVE_06/quot.xml 11774105 u ∞ +0 1 +0 0.04/0.04
AProVE_06/sizeChange.xml 11774108 u ∞ +0 1 +0 17.82/7.22
AProVE_06/tower.xml 11774104 u ∞ +0 1 +0 295.57/190.23
AProVE_06/tower_sizeChange.xml 11774109 u ∞ +0 1 +0 664.81/281.04
Secret_06_TRS/10.xml 11774130 s n1 +1 1 +0 0.09/0.10
Secret_06_TRS/4.xml 11774135 s n1 +1 1 +0 0.07/0.04
Secret_06_TRS/6.xml 11774117 s n1 +1 1 +0 0.08/0.04
Secret_06_TRS/addList.xml 11774122 u ∞ +0 1 +0 621.59/296.12
Secret_06_TRS/divExp.xml 11774121 u ∞ +0 1 +0 0.06/0.04
Secret_06_TRS/division.xml 11774128 u ∞ +0 1 +0 29.37/10.60
Secret_06_TRS/double.xml 11774120 u ∞ +0 1 +0 27.44/11.92
Secret_06_TRS/gen-1.xml 11774139 s n2 +1 1 +0 1.21/0.55
Secret_06_TRS/gen-17.xml 11774131 s n1 +1 1 +0 2.02/1.29
Secret_06_TRS/gen-28.xml 11774129 u ∞ +0 1 +0 31.11/10.51
Secret_06_TRS/logarithm.xml 11774127 u ∞ +0 1 +0 44.98/15.28
Secret_06_TRS/nrOfNodes.xml 11774134 u ∞ +0 1 +0 90.59/46.92
Secret_06_TRS/reverse.xml 11774123 u ∞ +0 1 +0 61.97/28.67
Secret_06_TRS/sumList.xml 11774137 u ∞ +0 1 +0 60.41/27.65
Secret_06_TRS/times.xml 11774132 u ∞ +0 1 +0 0.05/0.05
Secret_06_TRS/toList.xml 11774133 u ∞ +0 1 +0 137.06/71.69
Secret_06_TRS/tpa04.xml 11774136 u timeout (wallclock)
Secret_06_TRS/tpa05.xml 11774138 u timeout (wallclock)
Secret_06_TRS/tpa06.xml 11774118 u ∞ +0 1 +0 903.94/296.08
Secret_06_TRS/tpa07.xml 11774126 u ∞ +0 1 +0 672.45/296.20
Secret_06_TRS/tpa08.xml 11774119 u timeout (wallclock)
Secret_06_TRS/tpa09.xml 11774125 u timeout (wallclock)
Secret_06_TRS/tpa10.xml 11774124 u timeout (wallclock)
CiME_04/ack_prolog.xml 11774056 u ∞ +0 1 +0 23.30/9.71
CiME_04/append-hard.xml 11774049 u ∞ +0 1 +0 16.86/5.50
CiME_04/append-wrong.xml 11774066 u ∞ +0 1 +0 17.55/6.64
CiME_04/append.xml 11774057 s n2 +1 1 +0 2.48/0.88
CiME_04/big.xml 11774045 u ∞ +0 1 +0 884.41/296.04
CiME_04/dpqs.xml 11774060 s n1 +1 1 +0 0.12/0.10
CiME_04/fact-hard.xml 11774062 u ∞ +0 1 +0 62.57/32.88
CiME_04/filliatre.xml 11774055 u ∞ +0 1 +0 597.65/222.15
CiME_04/filliatre2.xml 11774059 u ∞ +0 1 +0 571.48/296.15
CiME_04/filliatre3.xml 11774067 u ∞ +0 1 +0 180.15/59.38
CiME_04/intersect.xml 11774058 u ∞ +0 1 +0 51.42/26.93
CiME_04/list-sum-prod-assoc-append.xml 11774061 u ∞ +0 1 +0 42.62/18.98
CiME_04/list-sum-prod-assoc.xml 11774063 u ∞ +0 1 +0 33.53/15.57
CiME_04/list-sum-prod-bin-assoc-distr-app.xml 11774054 u ∞ +0 1 +0 867.43/296.13
CiME_04/list-sum-prod-bin-assoc.xml 11774065 u ∞ +0 1 +0 862.71/296.07
CiME_04/list-sum-prod-bin.xml 11774046 u ∞ +0 1 +0 843.16/296.14
CiME_04/list-sum-prod.xml 11774050 u ∞ +0 1 +0 124.45/61.78
CiME_04/log2.xml 11774047 u ∞ +0 1 +0 1142.92/296.29
CiME_04/lse.xml 11774053 s n2 +1 1 +0 85.13/27.99
CiME_04/maude2.xml 11774052 u ∞ +0 1 +0 0.11/0.10
CiME_04/mucrl1.xml 11774048 u ∞ +0 1 +0 13.74/6.66
CiME_04/ternary-hard.xml 11774051 u ∞ +0 1 +0 823.42/296.12
CiME_04/ternary.xml 11774064 u ∞ +0 1 +0 1179.91/296.25
CiME_04/tree.xml 11774068 u timeout (wallclock)
Strategy_removed_CSR_05/Ex14_AEGL02.xml 11774091 u ∞ +0 1 +0 9.57/3.69
Strategy_removed_CSR_05/Ex15_Luc98.xml 11774072 u ∞ +0 1 +0 18.28/6.23
Strategy_removed_CSR_05/Ex1_2_AEL03.xml 11774078 u ∞ +0 1 +0 25.00/10.05
Strategy_removed_CSR_05/Ex1_2_Luc02c.xml 11774083 u ∞ +0 1 +0 7.26/2.45
Strategy_removed_CSR_05/Ex1_GL02a.xml 11774077 u ∞ +0 1 +0 19.53/7.61
Strategy_removed_CSR_05/Ex1_GM03.xml 11774075 u ∞ +0 1 +0 86.68/47.16
Strategy_removed_CSR_05/Ex1_Luc02b.xml 11774095 u ∞ +0 1 +0 15.90/6.39
Strategy_removed_CSR_05/Ex1_Zan97.xml 11774102 u ∞ +0 1 +0 193.76/83.80
Strategy_removed_CSR_05/Ex26_Luc03b.xml 11774099 u ∞ +0 1 +0 35.26/13.73
Strategy_removed_CSR_05/Ex2_Luc03b.xml 11774069 u ∞ +0 1 +0 18.72/8.16
Strategy_removed_CSR_05/Ex3_12_Luc96a.xml 11774103 u ∞ +0 1 +0 10.63/4.07
Strategy_removed_CSR_05/Ex3_2_Luc97.xml 11774082 u ∞ +0 1 +0 24.75/9.24
Strategy_removed_CSR_05/Ex3_3_25_Bor03.xml 11774081 u ∞ +0 1 +0 22.75/8.83
Strategy_removed_CSR_05/Ex49_GM04.xml 11774079 u ∞ +0 1 +0 759.47/296.12
Strategy_removed_CSR_05/Ex4_4_Luc96b.xml 11774086 u ∞ +0 1 +0 10.12/4.14
Strategy_removed_CSR_05/Ex4_7_15_Bor03.xml 11774101 u ∞ +0 1 +0 56.86/21.95
Strategy_removed_CSR_05/Ex4_7_37_Bor03.xml 11774090 u ∞ +0 1 +0 24.73/8.16
Strategy_removed_CSR_05/Ex4_7_56_Bor03.xml 11774080 u ∞ +0 1 +0 9.47/3.34
Strategy_removed_CSR_05/Ex4_7_77_Bor03.xml 11774074 u ∞ +0 1 +0 18.00/8.06
Strategy_removed_CSR_05/Ex4_Zan97.xml 11774094 u ∞ +0 1 +0 14.37/5.66
Strategy_removed_CSR_05/Ex5_7_Luc97.xml 11774073 u ∞ +0 1 +0 27.00/11.22
Strategy_removed_CSR_05/Ex5_Zan97.xml 11774096 u ∞ +0 1 +0 17.99/8.06
Strategy_removed_CSR_05/Ex6_15_AEL02.xml 11774100 u ∞ +0 1 +0 33.58/16.06
Strategy_removed_CSR_05/Ex6_9_Luc02c.xml 11774093 u ∞ +0 1 +0 14.21/4.89
Strategy_removed_CSR_05/Ex6_GM04.xml 11774070 u ∞ +0 1 +0 20.24/8.08
Strategy_removed_CSR_05/Ex6_Luc98.xml 11774085 u ∞ +0 1 +0 10.74/3.59
Strategy_removed_CSR_05/Ex7_BLR02.xml 11774098 u ∞ +0 1 +0 20.81/10.38
Strategy_removed_CSR_05/Ex8_BLR02.xml 11774088 u ∞ +0 1 +0 20.75/6.60
Strategy_removed_CSR_05/Ex9_BLR02.xml 11774089 u ∞ +0 1 +0 22.44/8.83
Strategy_removed_CSR_05/ExAppendixB_AEL03.xml 11774092 u ∞ +0 1 +0 30.40/13.64
Strategy_removed_CSR_05/ExConc_Zan97.xml 11774071 u ∞ +0 1 +0 19.32/8.08
Strategy_removed_CSR_05/ExIntrod_GM01.xml 11774084 u ∞ +0 1 +0 60.42/21.64
Strategy_removed_CSR_05/ExIntrod_GM04.xml 11774076 u ∞ +0 1 +0 137.85/73.22
Strategy_removed_CSR_05/ExIntrod_GM99.xml 11774087 u ∞ +0 1 +0 189.11/80.58
Strategy_removed_CSR_05/ExIntrod_Zan97.xml 11774097 u ∞ +0 1 +0 933.95/296.12
HirokawaMiddeldorp_04/n002.xml 11774753 u ∞ +0 1 +0 21.12/8.04
HirokawaMiddeldorp_04/n003.xml 11774748 u ∞ +0 1 +0 19.03/8.06
HirokawaMiddeldorp_04/n004.xml 11774749 u ∞ +0 1 +0 21.04/8.07
HirokawaMiddeldorp_04/n005.xml 11774752 u ∞ +0 1 +0 25.15/8.07
HirokawaMiddeldorp_04/n006.xml 11774740 u ∞ +0 1 +0 18.99/8.06
HirokawaMiddeldorp_04/n007.xml 11774743 u ∞ +0 1 +0 5.14/2.42
HirokawaMiddeldorp_04/t001.xml 11774741 u timeout (wallclock)
HirokawaMiddeldorp_04/t002.xml 11774754 u timeout (wallclock)
HirokawaMiddeldorp_04/t003.xml 11774747 u timeout (wallclock)
HirokawaMiddeldorp_04/t004.xml 11774746 u ∞ +0 1 +0 83.94/41.76
HirokawaMiddeldorp_04/t009.xml 11774742 u ∞ +0 1 +0 511.22/296.12
HirokawaMiddeldorp_04/t011.xml 11774744 s n1 +1 1 +0 0.59/0.22
HirokawaMiddeldorp_04/t012.xml 11774745 u ∞ +0 1 +0 528.29/296.05
HirokawaMiddeldorp_04/t013.xml 11774751 u ∞ +0 1 +0 38.84/16.75
HirokawaMiddeldorp_04/t014.xml 11774750 u ∞ +0 1 +0 757.92/296.04
Secret_05_TRS/aprove2.xml 11774761 u ∞ +0 1 +0 24.17/8.56
Secret_05_TRS/aprove3.xml 11774757 u ∞ +0 1 +0 31.13/11.76
Secret_05_TRS/aprove4.xml 11774758 u ∞ +0 1 +0 0.08/0.04
Secret_05_TRS/aprove5.xml 11774760 u ∞ +0 1 +0 45.16/22.71
Secret_05_TRS/cime2.xml 11774767 u ∞ +0 1 +0 70.96/23.06
Secret_05_TRS/cime3.xml 11774766 u ∞ +0 1 +0 0.09/0.07
Secret_05_TRS/cime4.xml 11774765 u ∞ +0 1 +0 12.98/4.81
Secret_05_TRS/cime5.xml 11774768 u ∞ +0 1 +0 1.31/0.35
Secret_05_TRS/tpa1.xml 11774769 u ∞ +0 1 +0 894.47/296.04
Secret_05_TRS/tpa2.xml 11774756 u ∞ +0 1 +0 639.82/296.14
Secret_05_TRS/tpa3.xml 11774762 u ∞ +0 1 +0 142.87/69.54
Secret_05_TRS/tpa4.xml 11774763 u timeout (wallclock)
Secret_05_TRS/tpa5.xml 11774755 u ∞ +0 1 +0 912.12/296.77
Secret_05_TRS/ttt1.xml 11774759 u ∞ +0 1 +0 19.28/10.37
Secret_05_TRS/ttt2.xml 11774764 u ∞ +0 1 +0 114.70/40.94
Rubio_04/bintrees.xml 11774668 s n1 +1 1 +0 0.68/0.21
Rubio_04/bn122.xml 11774650 s n2 +1 1 +0 0.86/0.52
Rubio_04/division.xml 11774653 u ∞ +0 1 +0 29.81/10.73
Rubio_04/elimdupl.xml 11774663 u ∞ +0 1 +0 32.73/13.59
Rubio_04/enno.xml 11774659 u ∞ +0 1 +0 36.14/17.47
Rubio_04/gcd.xml 11774670 u ∞ +0 1 +0 32.81/11.49
Rubio_04/gm.xml 11774662 u ∞ +0 1 +0 22.08/9.97
Rubio_04/gmnp.xml 11774671 s n1 +1 1 +0 0.05/0.03
Rubio_04/koen.xml 11774661 u ∞ +0 1 +0 0.04/0.04
Rubio_04/logarquot.xml 11774655 u ∞ +0 1 +0 24.98/10.37
Rubio_04/ma96.xml 11774652 u ∞ +0 1 +0 697.27/296.09
Rubio_04/mfp95.xml 11774658 s n1 +1 1 +0 0.03/0.03
Rubio_04/nestrec.xml 11774665 u ∞ +0 1 +0 250.78/88.17
Rubio_04/p266.xml 11774654 s n1 +1 1 +0 0.15/0.06
Rubio_04/polo2.xml 11774669 s n2 +1 1 +0 25.69/7.63
Rubio_04/prov.xml 11774651 u ∞ +0 1 +0 16.77/7.09
Rubio_04/quick.xml 11774672 u ∞ +0 1 +0 959.83/296.14
Rubio_04/quotminus.xml 11774657 u ∞ +0 1 +0 22.45/7.69
Rubio_04/revlist.xml 11774664 u ∞ +0 1 +0 714.28/296.03
Rubio_04/selsort.xml 11774667 u ∞ +0 1 +0 835.64/296.59
Rubio_04/test4.xml 11774660 s n1 +1 1 +0 0.03/0.03
Rubio_04/test829.xml 11774656 s n1 +1 1 +0 0.08/0.04
Rubio_04/wst99.xml 11774666 u ∞ +0 1 +0 56.30/20.46
AProVE_07/kabasci01.xml 11774730 u ∞ +0 1 +0 771.41/296.44
AProVE_07/kabasci02.xml 11774690 u ∞ +0 1 +0 0.11/0.07
AProVE_07/kabasci03.xml 11774699 u ∞ +0 1 +0 0.16/0.06
AProVE_07/kabasci04.xml 11774700 u ∞ +0 1 +0 774.15/296.12
AProVE_07/kabasci05.xml 11774687 u timeout (wallclock)
AProVE_07/otto01.xml 11774711 u timeout (wallclock)
AProVE_07/otto02.xml 11774703 u ∞ +0 1 +0 517.26/247.94
AProVE_07/otto03.xml 11774685 u ∞ +0 1 +0 18.15/7.12
AProVE_07/otto04.xml 11774684 u ∞ +0 1 +0 36.59/17.14
AProVE_07/otto05.xml 11774705 u ∞ +0 1 +0 22.46/8.66
AProVE_07/otto06.xml 11774709 u ∞ +0 1 +0 667.81/296.07
AProVE_07/otto07.xml 11774728 u ∞ +0 1 +0 16.75/7.33
AProVE_07/otto08.xml 11774714 u ∞ +0 1 +0 36.00/14.11
AProVE_07/otto09.xml 11774726 u ∞ +0 1 +0 24.90/9.84
AProVE_07/otto10.xml 11774719 u ∞ +0 1 +0 48.12/17.27
AProVE_07/otto11.xml 11774734 u ∞ +0 1 +0 38.53/17.39
AProVE_07/otto12.xml 11774676 u ∞ +0 1 +0 33.77/13.56
AProVE_07/otto13.xml 11774695 u ∞ +0 1 +0 67.91/31.33
AProVE_07/thiemann01.xml 11774689 u ∞ +0 1 +0 29.69/11.47
AProVE_07/thiemann02.xml 11774729 u timeout (wallclock)
AProVE_07/thiemann03.xml 11774708 u ∞ +0 1 +0 89.30/40.64
AProVE_07/thiemann04.xml 11774707 u timeout (wallclock)
AProVE_07/thiemann05.xml 11774731 u ∞ +0 1 +0 84.94/38.16
AProVE_07/thiemann06.xml 11774688 u ∞ +0 1 +0 41.91/16.00
AProVE_07/thiemann07.xml 11774701 u ∞ +0 1 +0 95.34/49.59
AProVE_07/thiemann08.xml 11774686 u ∞ +0 1 +0 27.47/11.01
AProVE_07/thiemann09.xml 11774702 u timeout (wallclock)
AProVE_07/thiemann10.xml 11774673 u ∞ +0 1 +0 24.34/8.91
AProVE_07/thiemann11.xml 11774698 u ∞ +0 1 +0 39.48/15.28
AProVE_07/thiemann12.xml 11774722 u ∞ +0 1 +0 27.76/10.87
AProVE_07/thiemann13.xml 11774733 u ∞ +0 1 +0 29.09/11.78
AProVE_07/thiemann14.xml 11774732 u ∞ +0 1 +0 549.69/296.12
AProVE_07/thiemann15.xml 11774723 u ∞ +0 1 +0 30.63/11.21
AProVE_07/thiemann16.xml 11774697 u ∞ +0 1 +0 940.80/296.14
AProVE_07/thiemann17.xml 11774674 u ∞ +0 1 +0 779.76/296.04
AProVE_07/thiemann18.xml 11774696 u ∞ +0 1 +0 84.72/41.92
AProVE_07/thiemann19.xml 11774675 u ∞ +0 1 +0 24.56/11.01
AProVE_07/thiemann20.xml 11774716 u ∞ +0 1 +0 53.12/21.73
AProVE_07/thiemann21.xml 11774739 u ∞ +0 1 +0 102.51/48.79
AProVE_07/thiemann22.xml 11774678 u ∞ +0 1 +0 29.81/10.67
AProVE_07/thiemann23.xml 11774694 u ∞ +0 1 +0 906.70/296.11
AProVE_07/thiemann24.xml 11774691 u ∞ +0 1 +0 30.17/11.58
AProVE_07/thiemann25.xml 11774679 u ∞ +0 1 +0 25.99/11.13
AProVE_07/thiemann26.xml 11774737 u ∞ +0 1 +0 27.39/10.18
AProVE_07/thiemann27.xml 11774717 u ∞ +0 1 +0 16.76/7.58
AProVE_07/thiemann28.xml 11774735 u ∞ +0 1 +0 737.79/296.12
AProVE_07/thiemann29.xml 11774720 u ∞ +0 1 +0 31.59/13.65
AProVE_07/thiemann30.xml 11774725 u ∞ +0 1 +0 883.25/296.72
AProVE_07/thiemann31.xml 11774713 u ∞ +0 1 +0 30.29/11.60
AProVE_07/thiemann32.xml 11774706 u ∞ +0 1 +0 670.40/296.07
AProVE_07/thiemann33.xml 11774682 u ∞ +0 1 +0 170.22/126.16
AProVE_07/thiemann34.xml 11774680 u ∞ +0 1 +0 25.86/10.89
AProVE_07/thiemann36.xml 11774712 u ∞ +0 1 +0 34.13/12.89
AProVE_07/thiemann37.xml 11774727 u timeout (wallclock)
AProVE_07/thiemann38.xml 11774710 u ∞ +0 1 +0 61.26/25.07
AProVE_07/thiemann40.xml 11774704 u ∞ +0 1 +0 17.16/6.65
AProVE_07/thiemann41.xml 11774683 u ∞ +0 1 +0 29.82/11.10
AProVE_07/wiehe01.xml 11774715 u ∞ +0 1 +0 0.07/0.08
AProVE_07/wiehe02.xml 11774693 u ∞ +0 1 +0 0.13/0.09
AProVE_07/wiehe03.xml 11774677 u ∞ +0 1 +0 0.30/0.11
AProVE_07/wiehe05.xml 11774692 u ∞ +0 1 +0 0.12/0.06
AProVE_07/wiehe06.xml 11774718 u ∞ +0 1 +0 0.14/0.06
AProVE_07/wiehe07.xml 11774738 u ∞ +0 1 +0 0.09/0.09
AProVE_07/wiehe08.xml 11774721 u ∞ +0 1 +0 0.10/0.05
AProVE_07/wiehe09.xml 11774736 u ∞ +0 1 +0 0.07/0.07
AProVE_07/wiehe11.xml 11774724 u ∞ +0 1 +0 0.13/0.06
AProVE_07/wiehe12.xml 11774681 u ∞ +0 1 +0 0.16/0.08
Endrullis_06/direct.xml 11774634 s n1 +1 1 +0 0.35/0.11
Secret_07_TRS/3.xml 11774641 u ∞ +0 1 +0 0.05/0.04
Secret_07_TRS/aprove01.xml 11774643 u ∞ +0 1 +0 58.24/26.01
Secret_07_TRS/aprove02.xml 11774642 u ∞ +0 1 +0 37.22/16.12
Secret_07_TRS/aprove03.xml 11774636 u timeout (wallclock)
Secret_07_TRS/aprove04.xml 11774637 u ∞ +0 1 +0 726.94/296.35
Secret_07_TRS/aprove05.xml 11774640 u ∞ +0 1 +0 70.29/30.30
Secret_07_TRS/aprove06.xml 11774644 u ∞ +0 1 +0 56.20/24.66
Secret_07_TRS/aprove07.xml 11774648 u ∞ +0 1 +0 63.97/27.50
Secret_07_TRS/aprove08.xml 11774645 u ∞ +0 1 +0 42.79/18.80
Secret_07_TRS/aprove09.xml 11774647 u ∞ +0 1 +0 42.69/17.61
Secret_07_TRS/aprove10.xml 11774646 u ∞ +0 1 +0 742.96/296.36
Secret_07_TRS/secret1.xml 11774649 u ∞ +0 1 +0 95.76/55.59
Secret_07_TRS/secret3.xml 11774638 u ∞ +0 1 +0 37.68/17.67
Secret_07_TRS/secret4.xml 11774639 u ∞ +0 1 +0 667.56/296.14
Secret_07_TRS/secret5.xml 11774635 u ∞ +0 1 +0 658.35/296.07
Waldmann_06/jwmatchb1.xml 11774623 s n1 +1 1 +0 0.03/0.03
Waldmann_06/jwmatchb2.xml 11774620 s n1 +1 1 +0 0.06/0.04
Waldmann_06/jwno1.xml 11774619 u ∞ +0 1 +0 32.69/12.96
Waldmann_06/jwno4.xml 11774622 u ∞ +0 1 +0 88.67/65.01
Waldmann_06/jwno6.xml 11774621 u ∞ +0 1 +0 71.01/49.61
AProVE_08/id_inc.xml 11774625 u ∞ +0 1 +0 0.11/0.08
AProVE_08/log.xml 11774624 u ∞ +0 1 +0 658.96/296.12
AProVE_08/parting01_reverse.xml 11774629 u ∞ +0 1 +0 901.57/296.70
AProVE_08/parting02_doublelist.xml 11774628 u ∞ +0 1 +0 899.20/296.76
AProVE_08/parting03_minsort.xml 11774630 u ∞ +0 1 +0 660.49/296.12
AProVE_08/parting04_maxsort_h.xml 11774632 u timeout (wallclock)
AProVE_08/parting05_maxsort.xml 11774626 u ∞ +0 1 +0 904.23/296.76
AProVE_08/round.xml 11774631 u ∞ +0 1 +0 0.10/0.05
AProVE_08/round_nonterm.xml 11774627 u ∞ +0 1 +0 0.04/0.03
AProVE_08/thiemann40_modified.xml 11774633 u ∞ +0 1 +0 27.97/12.28
TCT_12/polycounter-10.xml 11774959 u ∞ +0 1 +0 70.68/45.39
TCT_12/polycounter-5.xml 11774963 s n5 +1 1 +0 32.53/16.79
TCT_12/recursion-10.xml 11774960 u ∞ +0 1 +0 108.76/69.19
TCT_12/recursion-5.xml 11774961 u ∞ +0 1 +0 82.21/49.02
TCT_12/sat.xml 11774962 u ∞ +0 1 +0 252.83/79.76
Der95/06.xml 11774974 s n1 +1 1 +0 0.07/0.04
Der95/07.xml 11774970 s n1 +1 1 +0 0.06/0.03
Der95/08.xml 11774973 s n2 +1 1 +0 3.22/1.22
Der95/11.xml 11774972 s n2 +1 1 +0 23.95/7.26
Der95/12.xml 11774965 u ∞ +0 1 +0 20.40/7.50
Der95/18.xml 11774971 s n1 +1 1 +0 0.91/0.35
Der95/20.xml 11774966 u ∞ +0 1 +0 50.80/23.42
Der95/21.xml 11774964 u ∞ +0 1 +0 71.13/37.74
Der95/27.xml 11774967 s n1 +1 1 +0 0.08/0.04
Der95/31.xml 11774968 u ∞ +0 1 +0 21.91/8.34
Der95/32.xml 11774969 u ∞ +0 1 +0 20.70/8.89
Der95/33.xml 11774975 u ∞ +0 1 +0 860.83/296.49
Strategy_removed_mixed_05/ex1.xml 11774936 u ∞ +0 1 +0 22.24/8.09
Strategy_removed_mixed_05/ex2.xml 11774938 u ∞ +0 1 +0 7.53/3.12
Strategy_removed_mixed_05/ex3.xml 11774942 u ∞ +0 1 +0 23.47/8.06
Strategy_removed_mixed_05/ex4.xml 11774941 u ∞ +0 1 +0 65.12/25.76
Strategy_removed_mixed_05/ex5.xml 11774939 u ∞ +0 1 +0 14.75/8.06
Strategy_removed_mixed_05/ex6.xml 11774935 u ∞ +0 1 +0 0.04/0.03
Strategy_removed_mixed_05/ExSec11_1_Luc02a.xml 11774944 u ∞ +0 1 +0 27.77/10.40
Strategy_removed_mixed_05/muladd.xml 11774943 u ∞ +0 1 +0 8.76/2.82
Strategy_removed_mixed_05/test10.xml 11774945 u ∞ +0 1 +0 0.02/0.03
Strategy_removed_mixed_05/test76.xml 11774937 u ∞ +0 1 +0 12.29/5.60
Strategy_removed_mixed_05/test77.xml 11774933 u ∞ +0 1 +0 11.70/4.31
Strategy_removed_mixed_05/test830.xml 11774934 s n1 +1 1 +0 0.07/0.04
Strategy_removed_mixed_05/tricky1.xml 11774940 s 1 +1 1 +0 0.12/0.05
Zantema_05/z10.xml 11774950 u ∞ +0 1 +0 26.41/10.11
Zantema_05/z12.xml 11774956 u ∞ +0 1 +0 438.17/296.13
Zantema_05/z13.xml 11774955 u ∞ +0 1 +0 988.06/296.13
Zantema_05/z14.xml 11774954 u ∞ +0 1 +0 944.17/296.04
Zantema_05/z15.xml 11774957 u ∞ +0 1 +0 1111.19/296.17
Zantema_05/z16.xml 11774947 u ∞ +0 1 +0 977.79/296.15
Zantema_05/z17.xml 11774951 u ∞ +0 1 +0 606.46/296.03
Zantema_05/z18.xml 11774946 u ∞ +0 1 +0 1087.76/296.15
Zantema_05/z23.xml 11774949 u ∞ +0 1 +0 741.56/296.21
Zantema_05/z24.xml 11774948 u ∞ +0 1 +0 691.07/296.29
Zantema_05/z26.xml 11774953 s n1 +1 1 +0 0.06/0.05
Zantema_05/z27.xml 11774958 u ∞ +0 1 +0 14.71/6.58
Zantema_05/z28.xml 11774952 u ∞ +0 1 +0 28.28/11.15
AProVE_09_Inductive/div.xml 11774900 u ∞ +0 1 +0 35.40/13.27
AProVE_09_Inductive/divhard.xml 11774911 u ∞ +0 1 +0 38.70/13.79
AProVE_09_Inductive/gcd.xml 11774910 u ∞ +0 1 +0 32.18/12.77
AProVE_09_Inductive/gcd2.xml 11774901 u ∞ +0 1 +0 42.50/15.91
AProVE_09_Inductive/gcdhard.xml 11774907 u ∞ +0 1 +0 38.47/17.54
AProVE_09_Inductive/log.xml 11774908 u ∞ +0 1 +0 33.93/14.61
AProVE_09_Inductive/maxsort.xml 11774905 u ∞ +0 1 +0 903.21/296.74
AProVE_09_Inductive/maxsortcondition.xml 11774906 u ∞ +0 1 +0 39.08/17.44
AProVE_09_Inductive/minsort.xml 11774909 u ∞ +0 1 +0 904.23/296.63
AProVE_09_Inductive/mod.xml 11774903 u ∞ +0 1 +0 38.72/14.60
AProVE_09_Inductive/qsort.xml 11774899 u timeout (wallclock)
AProVE_09_Inductive/qsortlast.xml 11774902 u timeout (wallclock)
AProVE_09_Inductive/qsortmiddle.xml 11774904 u ∞ +0 1 +0 1101.28/296.14
AProVE_09_Inductive/zerolist.xml 11774912 u ∞ +0 1 +0 18.60/6.81
AProVE_04/AAECC-ring.xml 11774920 u timeout (wallclock)
AProVE_04/AAECC.xml 11774921 u timeout (wallclock)
AProVE_04/fac.xml 11774923 u ∞ +0 1 +0 68.35/37.52
AProVE_04/IJCAR_1.xml 11774927 u ∞ +0 1 +0 65.19/52.71
AProVE_04/IJCAR_12.xml 11774914 u ∞ +0 1 +0 26.21/9.30
AProVE_04/IJCAR_18.xml 11774929 u ∞ +0 1 +0 731.05/296.12
AProVE_04/IJCAR_26.xml 11774919 u ∞ +0 1 +0 741.48/296.13
AProVE_04/IJCAR_26a.xml 11774928 u ∞ +0 1 +0 725.56/296.10
AProVE_04/JFP_Ex31.xml 11774932 u ∞ +0 1 +0 903.17/296.13
AProVE_04/JFP_Ex51.xml 11774916 u ∞ +0 1 +0 57.97/22.55
AProVE_04/Liveness6.1.xml 11774915 u ∞ +0 1 +0 1135.44/296.14
AProVE_04/Liveness6.2.xml 11774930 u ∞ +0 1 +0 828.50/296.66
AProVE_04/Liveness6.3.xml 11774924 s n1 +1 1 +0 0.18/0.07
AProVE_04/Liveness6.4.xml 11774925 u ∞ +0 1 +0 926.99/296.06
AProVE_04/Liveness8.xml 11774926 s n1 +1 1 +0 0.07/0.04
AProVE_04/Liveness_WRS.xml 11774922 s n1 +1 1 +0 0.47/0.15
AProVE_04/LPAR_intlist.xml 11774918 u ∞ +0 1 +0 0.07/0.04
AProVE_04/rta1.xml 11774931 u ∞ +0 1 +0 931.79/296.12
AProVE_04/rta2.xml 11774913 u ∞ +0 1 +0 6.83/3.10
AProVE_04/rta3.xml 11774917 u ∞ +0 1 +0 17.52/7.35
AG01/#3.1.xml 11774808 u ∞ +0 1 +0 13.71/5.03
AG01/#3.10.xml 11774793 u ∞ +0 1 +0 886.86/297.42
AG01/#3.12.xml 11774780 u ∞ +0 1 +0 317.26/124.75
AG01/#3.13.xml 11774787 u timeout (wallclock)
AG01/#3.15.xml 11774782 s n1 +1 1 +0 0.91/0.25
AG01/#3.16.xml 11774813 u ∞ +0 1 +0 47.11/13.75
AG01/#3.17.xml 11774795 u timeout (wallclock)
AG01/#3.17a.xml 11774790 u timeout (wallclock)
AG01/#3.18.xml 11774811 u ∞ +0 1 +0 22.04/7.38
AG01/#3.19.xml 11774796 u ∞ +0 1 +0 31.30/13.53
AG01/#3.2.xml 11774779 u ∞ +0 1 +0 18.25/7.04
AG01/#3.22.xml 11774800 u timeout (wallclock)
AG01/#3.23.xml 11774806 u ∞ +0 1 +0 9.29/3.37
AG01/#3.24.xml 11774805 s n1 +1 1 +0 0.07/0.04
AG01/#3.26.xml 11774792 u ∞ +0 1 +0 150.80/55.02
AG01/#3.29.xml 11774776 u ∞ +0 1 +0 0.04/0.03
AG01/#3.31.xml 11774773 u ∞ +0 1 +0 31.74/20.72
AG01/#3.33.xml 11774802 s n1 +1 1 +0 0.05/0.03
AG01/#3.35.xml 11774817 s n1 +1 1 +0 0.04/0.03
AG01/#3.36.xml 11774772 u ∞ +0 1 +0 40.80/17.91
AG01/#3.37.xml 11774783 s n1 +1 1 +0 0.05/0.04
AG01/#3.38.xml 11774771 u ∞ +0 1 +0 47.74/20.26
AG01/#3.39.xml 11774784 u ∞ +0 1 +0 31.59/13.56
AG01/#3.4.xml 11774789 u ∞ +0 1 +0 24.88/8.43
AG01/#3.40.xml 11774816 u ∞ +0 1 +0 61.85/31.92
AG01/#3.41.xml 11774803 u ∞ +0 1 +0 22.25/9.16
AG01/#3.42.xml 11774785 u ∞ +0 1 +0 34.26/14.15
AG01/#3.47.xml 11774815 s n2 +1 1 +0 0.98/0.65
AG01/#3.48.xml 11774801 u ∞ +0 1 +0 891.11/296.48
AG01/#3.49.xml 11774818 u ∞ +0 1 +0 1085.67/296.12
AG01/#3.5.xml 11774775 u ∞ +0 1 +0 27.27/8.90
AG01/#3.51.xml 11774807 s n1 +1 1 +0 0.06/0.04
AG01/#3.52.xml 11774778 s n2 +1 1 +0 2.09/0.61
AG01/#3.53.xml 11774788 u ∞ +0 1 +0 42.97/21.85
AG01/#3.53a.xml 11774814 u ∞ +0 1 +0 0.03/0.04
AG01/#3.53b.xml 11774770 s n2 +1 1 +0 2.36/0.69
AG01/#3.54.xml 11774791 u ∞ +0 1 +0 0.03/0.03
AG01/#3.55.xml 11774777 u ∞ +0 1 +0 957.33/296.18
AG01/#3.56.xml 11774810 s n1 +1 1 +0 0.06/0.04
AG01/#3.57.xml 11774799 u timeout (wallclock)
AG01/#3.5a.xml 11774786 u ∞ +0 1 +0 31.90/10.89
AG01/#3.5b.xml 11774794 u ∞ +0 1 +0 37.84/14.08
AG01/#3.6.xml 11774809 u ∞ +0 1 +0 31.49/11.61
AG01/#3.6a.xml 11774804 u ∞ +0 1 +0 32.40/10.62
AG01/#3.6b.xml 11774774 u ∞ +0 1 +0 32.85/13.23
AG01/#3.7.xml 11774797 s n1 +1 1 +0 0.90/0.25
AG01/#3.8a.xml 11774781 u ∞ +0 1 +0 26.68/11.19
AG01/#3.8b.xml 11774812 u ∞ +0 1 +0 34.37/15.38
AG01/#4.30c.xml 11774798 u ∞ +0 1 +0 34.30/12.28
SK90/2.02.xml 11774842 s n1 +1 1 +0 0.09/0.04
SK90/2.03.xml 11774830 s n1 +1 1 +0 0.03/0.04
SK90/2.07.xml 11774898 s n2 +1 1 +0 13.08/3.43
SK90/2.09.xml 11774895 s n1 +1 1 +0 0.06/0.04
SK90/2.11.xml 11774880 s n1 +1 1 +0 0.05/0.04
SK90/2.12.xml 11774831 u ∞ +0 1 +0 62.76/17.97
SK90/2.13.xml 11774862 s n1 +1 1 +0 0.37/0.13
SK90/2.14.xml 11774861 s n1 +1 1 +0 0.05/0.04
SK90/2.15.xml 11774832 u ∞ +0 1 +0 12.93/5.40
SK90/2.16.xml 11774879 s n2 +1 1 +0 13.80/3.62
SK90/2.17.xml 11774872 s n2 +1 1 +0 0.64/0.44
SK90/2.18.xml 11774882 s n2 +1 1 +0 4.77/1.36
SK90/2.19.xml 11774869 s n2 +1 1 +0 8.99/2.43
SK90/2.20.xml 11774839 s n2 +1 1 +0 0.49/0.28
SK90/2.21.xml 11774854 u ∞ +0 1 +0 12.02/5.05
SK90/2.22.xml 11774864 u ∞ +0 1 +0 18.94/8.65
SK90/2.23.xml 11774887 u ∞ +0 1 +0 23.91/9.04
SK90/2.24.xml 11774886 u ∞ +0 1 +0 15.72/8.20
SK90/2.25.xml 11774866 u ∞ +0 1 +0 17.98/6.06
SK90/2.26.xml 11774853 u ∞ +0 1 +0 70.55/35.28
SK90/2.27.xml 11774841 u ∞ +0 1 +0 168.67/70.49
SK90/2.28.xml 11774859 u ∞ +0 1 +0 12.04/5.51
SK90/2.29.xml 11774836 s n2 +1 1 +0 7.06/2.11
SK90/2.30.xml 11774849 s n1 +1 1 +0 0.29/0.11
SK90/2.31.xml 11774821 s n1 +1 1 +0 0.09/0.08
SK90/2.36.xml 11774819 s n1 +1 1 +0 0.42/0.13
SK90/2.37.xml 11774851 s n2 +1 1 +0 0.36/0.25
SK90/2.38.xml 11774827 s n1 +1 1 +0 0.04/0.03
SK90/2.39.xml 11774846 u ∞ +0 1 +0 59.84/21.81
SK90/2.40.xml 11774893 s n2 +1 1 +0 15.93/4.19
SK90/2.41.xml 11774875 s n1 +1 1 +0 0.19/0.07
SK90/2.42.xml 11774847 s n1 +1 1 +0 0.05/0.03
SK90/2.43.xml 11774824 u ∞ +0 1 +0 213.60/120.35
SK90/2.44.xml 11774826 s n2 +1 1 +0 3.28/1.91
SK90/2.45.xml 11774845 u ∞ +0 1 +0 554.35/296.14
SK90/2.47.xml 11774890 s n1 +1 1 +0 0.03/0.03
SK90/2.48.xml 11774877 s n1 +1 1 +0 0.05/0.03
SK90/2.49.xml 11774889 s n1 +1 1 +0 0.06/0.04
SK90/2.50.xml 11774868 s n1 +1 1 +0 0.03/0.03
SK90/2.51.xml 11774885 u ∞ +0 1 +0 14.47/5.82
SK90/2.52.xml 11774837 u ∞ +0 1 +0 58.28/31.24
SK90/2.53.xml 11774856 s n1 +1 1 +0 0.02/0.02
SK90/2.54.xml 11774858 s n1 +1 1 +0 0.03/0.03
SK90/2.55.xml 11774835 u ∞ +0 1 +0 0.03/0.03
SK90/2.59.xml 11774865 u ∞ +0 1 +0 0.03/0.03
SK90/2.61.xml 11774860 u ∞ +0 1 +0 0.07/0.05
SK90/4.05.xml 11774833 s n2 +1 1 +0 1.58/0.50
SK90/4.06.xml 11774881 u ∞ +0 1 +0 22.28/9.22
SK90/4.07.xml 11774870 u ∞ +0 1 +0 0.06/0.04
SK90/4.09.xml 11774871 u ∞ +0 1 +0 0.04/0.04
SK90/4.10.xml 11774896 s n2 +1 1 +0 11.98/3.13
SK90/4.12.xml 11774844 s n1 +1 1 +0 0.26/0.08
SK90/4.13.xml 11774828 u ∞ +0 1 +0 12.46/5.62
SK90/4.16.xml 11774874 s n1 +1 1 +0 0.06/0.04
SK90/4.17.xml 11774897 u ∞ +0 1 +0 344.67/143.58
SK90/4.18.xml 11774873 s n2 +1 1 +0 6.97/1.94
SK90/4.22.xml 11774891 u ∞ +0 1 +0 18.65/8.22
SK90/4.24.xml 11774876 u ∞ +0 1 +0 724.64/296.11
SK90/4.25.xml 11774894 u ∞ +0 1 +0 0.06/0.05
SK90/4.26.xml 11774825 s n1 +1 1 +0 0.09/0.04
SK90/4.27.xml 11774848 u ∞ +0 1 +0 1174.95/296.14
SK90/4.28.xml 11774823 u ∞ +0 1 +0 0.18/0.10
SK90/4.29.xml 11774850 s n1 +1 1 +0 0.15/0.06
SK90/4.30.xml 11774834 s n1 +1 1 +0 0.09/0.05
SK90/4.31.xml 11774857 u ∞ +0 1 +0 25.60/11.64
SK90/4.34.xml 11774884 u ∞ +0 1 +0 287.35/162.26
SK90/4.35.xml 11774867 s n1 +1 1 +0 0.04/0.03
SK90/4.38.xml 11774855 s n1 +1 1 +0 0.05/0.03
SK90/4.42.xml 11774840 u ∞ +0 1 +0 22.42/9.13
SK90/4.43.xml 11774852 u ∞ +0 1 +0 46.20/16.41
SK90/4.45.xml 11774838 u ∞ +0 1 +0 0.05/0.05
SK90/4.47.xml 11774863 s n1 +1 1 +0 0.89/0.43
SK90/4.48.xml 11774883 u ∞ +0 1 +0 0.04/0.05
SK90/4.51.xml 11774878 u ∞ +0 1 +0 0.02/0.03
SK90/4.53.xml 11774820 u ∞ +0 1 +0 0.04/0.03
SK90/4.54.xml 11774822 u ∞ +0 1 +0 16.75/7.26
SK90/4.57.xml 11774888 u ∞ +0 1 +0 635.93/296.08
SK90/4.59.xml 11774892 u ∞ +0 1 +0 31.45/11.91
SK90/4.60.xml 11774843 u ∞ +0 1 +0 655.89/296.10
SK90/4.61.xml 11774829 u timeout (wallclock)
GTSSK07/cade01.xml 11774976 u ∞ +0 1 +0 15.64/6.42
GTSSK07/cade03.xml 11774988 u ∞ +0 1 +0 18.22/6.97
GTSSK07/cade04t.xml 11774982 u ∞ +0 1 +0 0.04/0.03
GTSSK07/cade05t.xml 11774979 u ∞ +0 1 +0 650.72/296.02
GTSSK07/cade06.xml 11774977 u ∞ +0 1 +0 904.38/296.13
GTSSK07/cade07.xml 11774984 u ∞ +0 1 +0 19.06/7.14
GTSSK07/cade08.xml 11774978 u timeout (wallclock)
GTSSK07/cade09.xml 11774983 u ∞ +0 1 +0 20.01/6.96
GTSSK07/cade10.xml 11774981 u ∞ +0 1 +0 18.94/6.28
GTSSK07/cade11.xml 11774985 u ∞ +0 1 +0 16.22/6.60
GTSSK07/cade12t.xml 11774989 u ∞ +0 1 +0 790.89/296.06
GTSSK07/cade13t.xml 11774991 u ∞ +0 1 +0 30.79/10.67
GTSSK07/cade14.xml 11774990 u ∞ +0 1 +0 27.67/10.13
GTSSK07/cade15.xml 11774987 u ∞ +0 1 +0 103.36/55.04
GTSSK07/cade16.xml 11774986 u ∞ +0 1 +0 62.08/33.01
GTSSK07/cade17.xml 11774980 u ∞ +0 1 +0 505.05/296.14
160