Termination Competition 2020: TRS Innermost41214

Job info CSV
benchmark muterm 6.0.3 default AProVE standard
raML/appendAll.raml.xml 11763533 YES 0.02/0.02 YES 3.81/2.40
raML/queue.raml.xml 11763532 YES 18.34/18.54 YES 14.21/4.88
raML/rationalPotential.raml.xml 11763530 YES 0.02/0.02 YES 6.89/1.65
raML/subtrees.raml.xml 11763531 YES 0.02/0.02 YES 3.97/2.59
Applicative_AG01_innermost/#4.10.xml 11763538 YES 0.02/0.02 YES 4.18/1.81
Applicative_AG01_innermost/#4.13.xml 11763544 YES 0.03/0.02 YES 4.39/1.86
Applicative_AG01_innermost/#4.15.xml 11763549 YES 0.03/0.03 YES 4.63/1.95
Applicative_AG01_innermost/#4.17.xml 11763537 YES 22.51/22.56 YES 4.63/2.06
Applicative_AG01_innermost/#4.19.xml 11763536 MAYBE 82.28/82.45 YES 4.65/1.95
Applicative_AG01_innermost/#4.2.xml 11763542 YES 0.03/0.03 YES 4.40/1.99
Applicative_AG01_innermost/#4.22.xml 11763539 MAYBE 206.27/206.76 YES 4.56/1.89
Applicative_AG01_innermost/#4.24.xml 11763534 YES 0.03/0.03 YES 4.60/1.94
Applicative_AG01_innermost/#4.26.xml 11763545 MAYBE 294.48/296.04 YES 5.51/2.19
Applicative_AG01_innermost/#4.28.xml 11763546 MAYBE 81.53/81.68 YES 4.49/1.90
Applicative_AG01_innermost/#4.3.xml 11763535 YES 0.02/0.02 YES 4.49/1.99
Applicative_AG01_innermost/#4.34.xml 11763540 YES 0.81/0.89 YES 5.09/2.05
Applicative_AG01_innermost/#4.36.xml 11763548 timeout (wallclock) [out] YES 6.56/2.66
Applicative_AG01_innermost/#4.5.xml 11763541 YES 0.02/0.02 YES 4.26/1.81
Applicative_AG01_innermost/#4.7.xml 11763547 YES 0.02/0.02 YES 4.25/1.93
Applicative_AG01_innermost/#4.8.xml 11763543 YES 21.67/21.84 YES 9.10/3.92
AG01_innermost/#4.12a.xml 11763244 YES 0.22/0.25 YES 4.07/2.92
AG01_innermost/#4.13.xml 11763214 YES 0.01/0.01 YES 3.49/1.60
AG01_innermost/#4.14.xml 11763216 YES 0.01/0.01 YES 3.49/1.64
AG01_innermost/#4.15.xml 11763226 YES 0.01/0.01 YES 3.68/1.69
AG01_innermost/#4.16.xml 11763238 YES 0.01/0.01 YES 3.49/1.58
AG01_innermost/#4.17.xml 11763243 YES 36.60/36.75 YES 3.78/1.85
AG01_innermost/#4.18.xml 11763235 YES 0.02/0.02 YES 4.78/2.00
AG01_innermost/#4.19.xml 11763246 YES 0.01/0.01 YES 3.72/1.73
AG01_innermost/#4.2.xml 11763236 YES 0.01/0.01 YES 3.61/1.81
AG01_innermost/#4.20.xml 11763224 YES 0.01/0.01 YES 3.19/1.67
AG01_innermost/#4.20a.xml 11763222 YES 0.03/0.04 YES 3.29/1.57
AG01_innermost/#4.21.xml 11763218 YES 0.01/0.01 YES 3.35/1.56
AG01_innermost/#4.22.xml 11763248 YES 0.01/0.01 YES 3.59/1.65
AG01_innermost/#4.23.xml 11763233 YES 0.03/0.03 YES 4.21/1.92
AG01_innermost/#4.24.xml 11763234 YES 0.01/0.01 YES 3.88/1.72
AG01_innermost/#4.25.xml 11763247 YES 0.12/0.16 YES 3.57/1.70
AG01_innermost/#4.26.xml 11763219 YES 0.07/0.09 YES 4.73/2.08
AG01_innermost/#4.27.xml 11763223 YES 0.05/0.06 YES 3.94/1.88
AG01_innermost/#4.28.xml 11763217 YES 0.05/0.05 YES 3.39/1.57
AG01_innermost/#4.29.xml 11763225 YES 0.12/0.12 YES 5.36/2.24
AG01_innermost/#4.3.xml 11763245 YES 0.01/0.01 YES 3.43/1.59
AG01_innermost/#4.30.xml 11763221 YES 203.73/204.36 YES 8.19/3.32
AG01_innermost/#4.30a.xml 11763227 YES 20.18/20.21 YES 4.77/2.55
AG01_innermost/#4.30b.xml 11763230 YES 81.80/81.97 YES 6.75/3.06
AG01_innermost/#4.31.xml 11763228 YES 87.50/87.72 YES 10.36/3.57
AG01_innermost/#4.32.xml 11763232 YES 0.01/0.01 YES 3.56/1.83
AG01_innermost/#4.33.xml 11763239 YES 0.07/0.07 YES 4.17/1.83
AG01_innermost/#4.34.xml 11763240 YES 0.06/0.06 YES 3.82/1.80
AG01_innermost/#4.35.xml 11763231 YES 0.36/0.56 YES 5.87/2.28
AG01_innermost/#4.36.xml 11763229 YES 0.11/0.10 YES 6.08/2.58
AG01_innermost/#4.37.xml 11763220 YES 0.05/0.07 YES 3.57/1.75
AG01_innermost/#4.37a.xml 11763241 YES 0.04/0.04 YES 3.93/1.72
AG01_innermost/#4.4.xml 11763242 YES 0.01/0.01 YES 3.51/1.70
AG01_innermost/#4.5.xml 11763237 YES 0.01/0.01 YES 5.18/2.01
AG01_innermost/#4.7.xml 11763215 YES 0.01/0.01 YES 3.49/1.60
Transformed_CSR_innermost_04/Ex14_AEGL02_C.xml 11763512 timeout (wallclock) [out] YES 3.72/2.62
Transformed_CSR_innermost_04/Ex14_AEGL02_GM.xml 11763432 YES 0.05/0.06 YES 4.86/2.41
Transformed_CSR_innermost_04/Ex14_AEGL02_iGM.xml 11763264 YES 0.72/0.80 YES 7.16/2.84
Transformed_CSR_innermost_04/Ex14_Luc06_C.xml 11763467 timeout (wallclock) [out] YES 4.84/2.01
Transformed_CSR_innermost_04/Ex14_Luc06_GM.xml 11763280 YES 125.32/125.71 YES 4.09/1.86
Transformed_CSR_innermost_04/Ex14_Luc06_iGM.xml 11763439 timeout (wallclock) [out] YES 6.57/2.54
Transformed_CSR_innermost_04/Ex15_Luc06_C.xml 11763298 YES 91.59/92.33 YES 3.73/1.69
Transformed_CSR_innermost_04/Ex15_Luc06_GM.xml 11763289 YES 0.01/0.01 YES 3.41/1.59
Transformed_CSR_innermost_04/Ex15_Luc06_iGM.xml 11763352 YES 0.04/0.05 YES 3.50/1.68
Transformed_CSR_innermost_04/Ex15_Luc98_C.xml 11763274 YES 0.21/0.21 YES 3.75/1.89
Transformed_CSR_innermost_04/Ex15_Luc98_GM.xml 11763418 YES 0.19/0.19 YES 4.53/1.99
Transformed_CSR_innermost_04/Ex15_Luc98_iGM.xml 11763502 YES 0.71/0.81 YES 8.80/3.15
Transformed_CSR_innermost_04/Ex16_Luc06_C.xml 11763505 timeout (wallclock) [out] YES 3.47/2.78
Transformed_CSR_innermost_04/Ex16_Luc06_GM.xml 11763265 YES 0.01/0.01 YES 3.75/1.78
Transformed_CSR_innermost_04/Ex16_Luc06_iGM.xml 11763476 timeout (wallclock) [out] YES 4.27/1.92
Transformed_CSR_innermost_04/Ex18_Luc06_C.xml 11763322 YES 0.06/0.06 YES 3.91/1.72
Transformed_CSR_innermost_04/Ex18_Luc06_GM.xml 11763348 YES 0.01/0.01 YES 3.37/1.59
Transformed_CSR_innermost_04/Ex18_Luc06_iGM.xml 11763296 YES 0.04/0.06 YES 3.44/1.63
Transformed_CSR_innermost_04/Ex18_Luc06_L.xml 11763382 YES 0.01/0.01 YES 3.24/2.20
Transformed_CSR_innermost_04/Ex1_2_AEL03_C.xml 11763416 timeout (wallclock) [out] YES 4.57/1.88
Transformed_CSR_innermost_04/Ex1_2_AEL03_GM.xml 11763451 timeout (wallclock) [out] YES 175.38/48.70
Transformed_CSR_innermost_04/Ex1_2_AEL03_iGM.xml 11763414 timeout (wallclock) [out] YES 121.42/43.39
Transformed_CSR_innermost_04/Ex1_2_Luc02c_C.xml 11763385 YES 0.10/0.09 YES 4.86/2.04
Transformed_CSR_innermost_04/Ex1_2_Luc02c_GM.xml 11763493 YES 0.40/0.54 YES 9.53/3.50
Transformed_CSR_innermost_04/Ex1_2_Luc02c_iGM.xml 11763376 YES 0.92/1.33 YES 9.68/3.41
Transformed_CSR_innermost_04/Ex1_GL02a_C.xml 11763488 YES 7.87/7.98 YES 3.79/1.73
Transformed_CSR_innermost_04/Ex1_GL02a_GM.xml 11763384 YES 0.02/0.02 YES 3.99/1.74
Transformed_CSR_innermost_04/Ex1_GL02a_iGM.xml 11763378 YES 1.11/1.20 YES 4.57/2.09
Transformed_CSR_innermost_04/Ex1_GM03_C.xml 11763527 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex1_GM03_GM.xml 11763357 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex1_GM03_iGM.xml 11763386 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex1_GM99_C.xml 11763404 timeout (wallclock) [out] YES 3.56/1.63
Transformed_CSR_innermost_04/Ex1_GM99_GM.xml 11763413 YES 0.04/0.04 YES 4.10/1.81
Transformed_CSR_innermost_04/Ex1_GM99_iGM.xml 11763487 timeout (wallclock) [out] YES 9.65/3.66
Transformed_CSR_innermost_04/Ex1_Luc02b_C.xml 11763411 timeout (wallclock) [out] YES 3.84/1.73
Transformed_CSR_innermost_04/Ex1_Luc02b_GM.xml 11763307 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex1_Luc02b_iGM.xml 11763369 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex1_Luc04b_C.xml 11763507 YES 1.57/1.67 YES 3.82/1.72
Transformed_CSR_innermost_04/Ex1_Luc04b_GM.xml 11763509 YES 0.75/0.80 YES 6.30/2.44
Transformed_CSR_innermost_04/Ex1_Luc04b_iGM.xml 11763300 YES 4.32/4.53 YES 10.09/3.54
Transformed_CSR_innermost_04/Ex1_Zan97_C.xml 11763318 YES 72.04/72.23 YES 9.11/3.11
Transformed_CSR_innermost_04/Ex1_Zan97_GM.xml 11763320 YES 0.03/0.05 YES 6.76/1.68
Transformed_CSR_innermost_04/Ex1_Zan97_iGM.xml 11763282 YES 0.04/0.05 YES 3.38/1.67
Transformed_CSR_innermost_04/Ex23_Luc06_C.xml 11763395 YES 0.08/0.08 YES 3.53/1.62
Transformed_CSR_innermost_04/Ex23_Luc06_GM.xml 11763458 YES 0.01/0.01 YES 3.33/1.56
Transformed_CSR_innermost_04/Ex23_Luc06_iGM.xml 11763396 YES 0.02/0.02 YES 3.62/1.70
Transformed_CSR_innermost_04/Ex23_Luc06_L.xml 11763304 YES 0.01/0.01 YES 3.33/1.54
Transformed_CSR_innermost_04/Ex24_GM04_C.xml 11763335 timeout (wallclock) [out] YES 3.68/1.68
Transformed_CSR_innermost_04/Ex24_GM04_GM.xml 11763305 YES 0.01/0.01 YES 3.59/1.63
Transformed_CSR_innermost_04/Ex24_GM04_iGM.xml 11763525 YES 0.72/1.27 YES 4.20/2.02
Transformed_CSR_innermost_04/Ex24_Luc06_C.xml 11763477 timeout (wallclock) [out] YES 3.70/1.69
Transformed_CSR_innermost_04/Ex24_Luc06_GM.xml 11763423 YES 0.01/0.01 YES 3.94/1.76
Transformed_CSR_innermost_04/Ex24_Luc06_iGM.xml 11763275 timeout (wallclock) [out] YES 4.38/1.93
Transformed_CSR_innermost_04/Ex25_Luc06_C.xml 11763262 YES 0.10/0.13 YES 3.79/1.67
Transformed_CSR_innermost_04/Ex25_Luc06_GM.xml 11763428 YES 0.01/0.01 YES 3.27/1.66
Transformed_CSR_innermost_04/Ex25_Luc06_iGM.xml 11763494 YES 0.09/0.09 YES 11.63/3.94
Transformed_CSR_innermost_04/Ex25_Luc06_L.xml 11763364 YES 0.01/0.01 YES 6.33/1.66
Transformed_CSR_innermost_04/Ex26_Luc03b_C.xml 11763403 YES 0.26/0.26 YES 4.22/1.80
Transformed_CSR_innermost_04/Ex26_Luc03b_GM.xml 11763429 YES 0.21/0.28 YES 6.23/2.50
Transformed_CSR_innermost_04/Ex26_Luc03b_iGM.xml 11763268 YES 0.72/0.72 YES 14.81/4.95
Transformed_CSR_innermost_04/Ex26_Luc03b_L.xml 11763313 YES 0.01/0.01 YES 3.47/1.55
Transformed_CSR_innermost_04/Ex2_Luc02a_C.xml 11763516 timeout (wallclock) [out] YES 3.94/2.47
Transformed_CSR_innermost_04/Ex2_Luc02a_GM.xml 11763365 YES 176.03/183.90 YES 8.81/3.06
Transformed_CSR_innermost_04/Ex2_Luc02a_iGM.xml 11763337 timeout (wallclock) [out] YES 12.12/4.16
Transformed_CSR_innermost_04/Ex2_Luc02a_L.xml 11763443 YES 0.01/0.01 YES 3.78/1.75
Transformed_CSR_innermost_04/Ex2_Luc03b_C.xml 11763340 YES 0.27/0.27 YES 4.00/1.85
Transformed_CSR_innermost_04/Ex2_Luc03b_GM.xml 11763469 YES 0.18/0.18 YES 5.69/2.28
Transformed_CSR_innermost_04/Ex2_Luc03b_iGM.xml 11763460 YES 0.43/0.43 YES 11.98/4.12
Transformed_CSR_innermost_04/Ex2_Luc03b_L.xml 11763283 YES 0.01/0.01 YES 3.57/1.67
Transformed_CSR_innermost_04/Ex3_12_Luc96a_C.xml 11763433 timeout (wallclock) [out] YES 3.63/1.71
Transformed_CSR_innermost_04/Ex3_12_Luc96a_GM.xml 11763504 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex3_12_Luc96a_iGM.xml 11763524 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex3_2_Luc97_C.xml 11763271 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex3_2_Luc97_GM.xml 11763417 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex3_2_Luc97_iGM.xml 11763496 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex3_3_25_Bor03_C.xml 11763299 YES 0.21/0.20 YES 3.99/1.75
Transformed_CSR_innermost_04/Ex3_3_25_Bor03_GM.xml 11763314 YES 0.32/0.33 YES 8.65/3.06
Transformed_CSR_innermost_04/Ex3_3_25_Bor03_iGM.xml 11763481 YES 0.49/0.48 YES 10.46/4.67
Transformed_CSR_innermost_04/Ex3_3_25_Bor03_L.xml 11763393 YES 0.01/0.01 YES 3.60/1.63
Transformed_CSR_innermost_04/Ex49_GM04_C.xml 11763522 YES 3.28/3.29 YES 4.06/1.75
Transformed_CSR_innermost_04/Ex49_GM04_GM.xml 11763311 YES 0.16/0.16 YES 6.08/2.38
Transformed_CSR_innermost_04/Ex49_GM04_iGM.xml 11763327 YES 0.47/0.47 YES 8.01/3.01
Transformed_CSR_innermost_04/Ex4_4_Luc96b_C.xml 11763269 YES 0.07/0.07 YES 3.96/1.75
Transformed_CSR_innermost_04/Ex4_4_Luc96b_GM.xml 11763351 YES 0.06/0.06 YES 4.63/2.05
Transformed_CSR_innermost_04/Ex4_4_Luc96b_iGM.xml 11763315 YES 0.05/0.05 YES 4.58/1.97
Transformed_CSR_innermost_04/Ex4_4_Luc96b_L.xml 11763373 YES 0.01/0.01 YES 3.29/1.58
Transformed_CSR_innermost_04/Ex4_7_15_Bor03_C.xml 11763523 YES 82.47/82.85 YES 3.64/1.66
Transformed_CSR_innermost_04/Ex4_7_15_Bor03_GM.xml 11763391 YES 0.03/0.04 YES 4.49/2.03
Transformed_CSR_innermost_04/Ex4_7_15_Bor03_iGM.xml 11763297 YES 0.53/0.54 YES 7.73/2.92
Transformed_CSR_innermost_04/Ex4_7_15_Bor03_L.xml 11763447 YES 0.05/0.06 YES 3.47/1.58
Transformed_CSR_innermost_04/Ex4_7_37_Bor03_C.xml 11763474 timeout (wallclock) [out] YES 4.78/1.99
Transformed_CSR_innermost_04/Ex4_7_37_Bor03_GM.xml 11763254 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex4_7_37_Bor03_iGM.xml 11763331 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex4_7_56_Bor03_C.xml 11763329 timeout (wallclock) [out] YES 3.72/1.78
Transformed_CSR_innermost_04/Ex4_7_56_Bor03_GM.xml 11763437 timeout (wallclock) [out] YES 14.43/4.47
Transformed_CSR_innermost_04/Ex4_7_56_Bor03_iGM.xml 11763324 timeout (wallclock) [out] YES 17.12/5.39
Transformed_CSR_innermost_04/Ex4_7_77_Bor03_C.xml 11763529 YES 0.15/0.17 YES 3.45/1.68
Transformed_CSR_innermost_04/Ex4_7_77_Bor03_GM.xml 11763492 YES 0.04/0.05 YES 3.54/1.69
Transformed_CSR_innermost_04/Ex4_7_77_Bor03_iGM.xml 11763431 YES 0.19/0.19 YES 4.33/1.86
Transformed_CSR_innermost_04/Ex4_DLMMU04_C.xml 11763473 timeout (wallclock) [out] YES 6.62/2.42
Transformed_CSR_innermost_04/Ex4_DLMMU04_GM.xml 11763456 timeout (wallclock) [out] YES 52.13/14.33
Transformed_CSR_innermost_04/Ex4_DLMMU04_iGM.xml 11763363 timeout (wallclock) [out] YES 86.73/28.59
Transformed_CSR_innermost_04/Ex4_Zan97_C.xml 11763463 timeout (wallclock) [out] YES 7.36/1.69
Transformed_CSR_innermost_04/Ex4_Zan97_GM.xml 11763267 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex4_Zan97_iGM.xml 11763253 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex5_7_Luc97_C.xml 11763259 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex5_7_Luc97_GM.xml 11763334 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex5_7_Luc97_iGM.xml 11763291 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex5_DLMMU04_C.xml 11763323 YES 2.11/2.12 YES 4.79/1.96
Transformed_CSR_innermost_04/Ex5_DLMMU04_GM.xml 11763356 YES 3.75/3.96 YES 9.02/3.21
Transformed_CSR_innermost_04/Ex5_DLMMU04_iGM.xml 11763398 YES 19.31/21.31 YES 20.32/6.66
Transformed_CSR_innermost_04/Ex5_Zan97_C.xml 11763375 YES 2.82/3.24 YES 3.51/1.70
Transformed_CSR_innermost_04/Ex5_Zan97_GM.xml 11763251 YES 1.32/1.43 YES 4.49/2.84
Transformed_CSR_innermost_04/Ex5_Zan97_iGM.xml 11763514 YES 3.92/4.39 YES 5.87/2.55
Transformed_CSR_innermost_04/Ex6_15_AEL02_C.xml 11763405 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex6_15_AEL02_GM.xml 11763358 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex6_15_AEL02_iGM.xml 11763438 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex6_9_Luc02c_C.xml 11763255 YES 0.14/0.14 YES 4.05/1.81
Transformed_CSR_innermost_04/Ex6_9_Luc02c_GM.xml 11763520 YES 35.14/36.75 YES 8.92/3.23
Transformed_CSR_innermost_04/Ex6_9_Luc02c_iGM.xml 11763377 YES 67.97/69.57 YES 15.79/5.20
Transformed_CSR_innermost_04/Ex6_GM04_C.xml 11763301 YES 0.06/0.06 YES 3.76/1.69
Transformed_CSR_innermost_04/Ex6_GM04_GM.xml 11763338 YES 0.01/0.01 YES 3.39/1.65
Transformed_CSR_innermost_04/Ex6_GM04_iGM.xml 11763501 YES 0.01/0.01 YES 3.51/1.58
Transformed_CSR_innermost_04/Ex6_Luc98_C.xml 11763465 YES 0.12/0.12 YES 3.79/1.67
Transformed_CSR_innermost_04/Ex6_Luc98_GM.xml 11763292 YES 0.09/0.12 YES 5.32/2.20
Transformed_CSR_innermost_04/Ex6_Luc98_iGM.xml 11763387 YES 0.14/0.15 YES 7.12/2.71
Transformed_CSR_innermost_04/Ex6_Luc98_L.xml 11763510 YES 0.01/0.01 YES 3.74/2.24
Transformed_CSR_innermost_04/Ex7_BLR02_C.xml 11763383 timeout (wallclock) [out] YES 4.09/2.00
Transformed_CSR_innermost_04/Ex7_BLR02_GM.xml 11763400 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex7_BLR02_iGM.xml 11763309 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex8_BLR02_C.xml 11763381 timeout (wallclock) [out] YES 3.95/1.92
Transformed_CSR_innermost_04/Ex8_BLR02_GM.xml 11763326 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex8_BLR02_iGM.xml 11763286 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex9_BLR02_C.xml 11763461 YES 0.37/0.40 YES 4.05/1.75
Transformed_CSR_innermost_04/Ex9_BLR02_GM.xml 11763319 YES 0.19/0.18 YES 6.61/2.46
Transformed_CSR_innermost_04/Ex9_BLR02_iGM.xml 11763503 YES 0.54/0.53 YES 13.76/4.72
Transformed_CSR_innermost_04/Ex9_BLR02_L.xml 11763506 YES 0.01/0.01 YES 3.40/1.55
Transformed_CSR_innermost_04/Ex9_Luc04_C.xml 11763515 timeout (wallclock) [out] YES 3.63/2.87
Transformed_CSR_innermost_04/Ex9_Luc04_GM.xml 11763490 timeout (wallclock) [out] YES 5.37/2.21
Transformed_CSR_innermost_04/Ex9_Luc04_iGM.xml 11763316 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/Ex9_Luc06_C.xml 11763452 timeout (wallclock) [out] YES 4.06/2.68
Transformed_CSR_innermost_04/Ex9_Luc06_GM.xml 11763471 YES 0.03/0.05 YES 3.84/1.67
Transformed_CSR_innermost_04/Ex9_Luc06_iGM.xml 11763497 YES 9.72/9.83 YES 4.38/2.04
Transformed_CSR_innermost_04/ExAppendixB_AEL03_C.xml 11763260 timeout (wallclock) [out] YES 4.70/1.99
Transformed_CSR_innermost_04/ExAppendixB_AEL03_GM.xml 11763410 timeout (wallclock) [out] YES 167.13/47.28
Transformed_CSR_innermost_04/ExAppendixB_AEL03_iGM.xml 11763436 timeout (wallclock) [out] YES 149.54/50.75
Transformed_CSR_innermost_04/ExConc_Zan97_C.xml 11763325 YES 0.13/0.12 YES 3.67/1.69
Transformed_CSR_innermost_04/ExConc_Zan97_GM.xml 11763499 YES 0.01/0.01 YES 3.44/1.56
Transformed_CSR_innermost_04/ExConc_Zan97_iGM.xml 11763407 YES 0.02/0.02 YES 3.72/1.69
Transformed_CSR_innermost_04/ExConc_Zan97_L.xml 11763388 YES 0.01/0.01 YES 3.39/1.61
Transformed_CSR_innermost_04/ExIntrod_GM01_C.xml 11763419 YES 2.11/2.12 YES 4.27/2.00
Transformed_CSR_innermost_04/ExIntrod_GM01_GM.xml 11763332 YES 1.56/1.69 YES 7.15/2.73
Transformed_CSR_innermost_04/ExIntrod_GM01_iGM.xml 11763392 YES 3.71/4.35 YES 11.05/3.76
Transformed_CSR_innermost_04/ExIntrod_GM04_C.xml 11763310 YES 6.26/6.29 YES 4.10/2.62
Transformed_CSR_innermost_04/ExIntrod_GM04_GM.xml 11763479 YES 0.11/0.12 YES 5.10/2.25
Transformed_CSR_innermost_04/ExIntrod_GM04_iGM.xml 11763261 YES 1.98/2.22 YES 8.31/3.00
Transformed_CSR_innermost_04/ExIntrod_GM99_C.xml 11763350 timeout (wallclock) [out] YES 4.31/1.83
Transformed_CSR_innermost_04/ExIntrod_GM99_GM.xml 11763462 timeout (wallclock) [out] YES 81.22/21.65
Transformed_CSR_innermost_04/ExIntrod_GM99_iGM.xml 11763276 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/ExIntrod_Zan97_C.xml 11763257 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/ExIntrod_Zan97_GM.xml 11763521 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/ExIntrod_Zan97_iGM.xml 11763270 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/ExProp7_Luc06_C.xml 11763402 YES 65.76/66.04 YES 3.70/1.79
Transformed_CSR_innermost_04/ExProp7_Luc06_GM.xml 11763336 YES 0.18/0.20 YES 4.59/2.13
Transformed_CSR_innermost_04/ExProp7_Luc06_iGM.xml 11763517 YES 0.68/0.75 YES 8.48/3.27
Transformed_CSR_innermost_04/ExProp7_Luc06_L.xml 11763312 YES 0.04/0.06 YES 3.35/1.54
Transformed_CSR_innermost_04/ExSec11_1_Luc02a_C.xml 11763491 timeout (wallclock) [out] YES 4.08/2.16
Transformed_CSR_innermost_04/ExSec11_1_Luc02a_GM.xml 11763415 timeout (wallclock) [out] YES 8.85/3.28
Transformed_CSR_innermost_04/ExSec11_1_Luc02a_iGM.xml 11763279 timeout (wallclock) [out] YES 13.79/4.51
Transformed_CSR_innermost_04/ExSec11_1_Luc02a_L.xml 11763453 YES 0.02/0.02 YES 3.84/1.90
Transformed_CSR_innermost_04/ExSec4_2_DLMMU04_C.xml 11763500 timeout (wallclock) [out] YES 4.10/1.80
Transformed_CSR_innermost_04/ExSec4_2_DLMMU04_GM.xml 11763353 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/ExSec4_2_DLMMU04_iGM.xml 11763519 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/LengthOfFiniteLists_complete_C.xml 11763406 timeout (wallclock) [out] YES 156.75/47.36
Transformed_CSR_innermost_04/LengthOfFiniteLists_complete_GM.xml 11763346 YES 20.77/21.55 YES 22.84/7.16
Transformed_CSR_innermost_04/LengthOfFiniteLists_complete_iGM.xml 11763256 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/LengthOfFiniteLists_complete_noand_C.xml 11763347 timeout (wallclock) [out] YES 9.68/3.36
Transformed_CSR_innermost_04/LengthOfFiniteLists_complete_noand_GM.xml 11763450 YES 1.54/1.57 YES 24.51/7.47
Transformed_CSR_innermost_04/LengthOfFiniteLists_complete_noand_iGM.xml 11763446 timeout (wallclock) [out] YES 434.74/164.3
Transformed_CSR_innermost_04/LengthOfFiniteLists_nokinds_C.xml 11763380 timeout (wallclock) [out] YES 6.12/2.32
Transformed_CSR_innermost_04/LengthOfFiniteLists_nokinds_GM.xml 11763480 YES 0.30/0.30 YES 5.86/2.38
Transformed_CSR_innermost_04/LengthOfFiniteLists_nokinds_iGM.xml 11763266 timeout (wallclock) [out] YES 111.10/43.66
Transformed_CSR_innermost_04/LengthOfFiniteLists_nokinds_noand_C.xml 11763272 timeout (wallclock) [out] YES 6.20/2.39
Transformed_CSR_innermost_04/LengthOfFiniteLists_nokinds_noand_GM.xml 11763328 YES 0.21/0.21 YES 9.01/3.21
Transformed_CSR_innermost_04/LengthOfFiniteLists_nokinds_noand_iGM.xml 11763394 YES 243.91/245.74 YES 65.49/22.80
Transformed_CSR_innermost_04/LengthOfFiniteLists_nosorts_C.xml 11763390 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/LengthOfFiniteLists_nosorts_GM.xml 11763273 timeout (wallclock) [out] NO 5.42/2.83
Transformed_CSR_innermost_04/LengthOfFiniteLists_nosorts_iGM.xml 11763263 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/LengthOfFiniteLists_nosorts_noand_C.xml 11763445 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/LengthOfFiniteLists_nosorts_noand_GM.xml 11763371 timeout (wallclock) [out] NO 10.07/3.64
Transformed_CSR_innermost_04/LengthOfFiniteLists_nosorts_noand_iGM.xml 11763528 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/LISTUTILITIES_complete_C.xml 11763485 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/LISTUTILITIES_complete_GM.xml 11763284 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/LISTUTILITIES_complete_iGM.xml 11763430 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/LISTUTILITIES_complete_noand_C.xml 11763457 timeout (wallclock) [out] YES 12.81/4.16
Transformed_CSR_innermost_04/LISTUTILITIES_complete_noand_GM.xml 11763339 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/LISTUTILITIES_complete_noand_iGM.xml 11763359 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/LISTUTILITIES_nokinds_C.xml 11763252 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/LISTUTILITIES_nokinds_GM.xml 11763399 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/LISTUTILITIES_nokinds_iGM.xml 11763361 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/LISTUTILITIES_nokinds_noand_C.xml 11763448 timeout (wallclock) [out] YES 7.16/2.57
Transformed_CSR_innermost_04/LISTUTILITIES_nokinds_noand_GM.xml 11763470 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/LISTUTILITIES_nokinds_noand_iGM.xml 11763427 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/LISTUTILITIES_nosorts_C.xml 11763258 timeout (wallclock) [out] YES 4.26/1.79
Transformed_CSR_innermost_04/LISTUTILITIES_nosorts_GM.xml 11763455 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/LISTUTILITIES_nosorts_iGM.xml 11763372 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/LISTUTILITIES_nosorts_noand_C.xml 11763294 timeout (wallclock) [out] YES 4.88/2.11
Transformed_CSR_innermost_04/LISTUTILITIES_nosorts_noand_GM.xml 11763440 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/LISTUTILITIES_nosorts_noand_iGM.xml 11763285 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/MYNAT_complete_C.xml 11763511 timeout (wallclock) [out] YES 11.42/3.70
Transformed_CSR_innermost_04/MYNAT_complete_GM.xml 11763281 timeout (wallclock) [out] YES 6.85/2.72
Transformed_CSR_innermost_04/MYNAT_complete_iGM.xml 11763483 timeout (wallclock) [out] YES 8.72/3.00
Transformed_CSR_innermost_04/MYNAT_complete_noand_C.xml 11763401 timeout (wallclock) [out] YES 6.78/2.56
Transformed_CSR_innermost_04/MYNAT_complete_noand_GM.xml 11763295 timeout (wallclock) [out] YES 40.91/12.57
Transformed_CSR_innermost_04/MYNAT_complete_noand_iGM.xml 11763341 timeout (wallclock) [out] YES 740.95/265.69
Transformed_CSR_innermost_04/MYNAT_nokinds_C.xml 11763374 timeout (wallclock) [out] YES 6.40/2.38
Transformed_CSR_innermost_04/MYNAT_nokinds_GM.xml 11763368 timeout (wallclock) [out] YES 4.92/2.07
Transformed_CSR_innermost_04/MYNAT_nokinds_iGM.xml 11763360 timeout (wallclock) [out] YES 6.91/2.62
Transformed_CSR_innermost_04/MYNAT_nokinds_noand_C.xml 11763306 timeout (wallclock) [out] YES 4.60/2.00
Transformed_CSR_innermost_04/MYNAT_nokinds_noand_GM.xml 11763250 YES 107.84/110.49 YES 15.61/4.84
Transformed_CSR_innermost_04/MYNAT_nokinds_noand_iGM.xml 11763468 timeout (wallclock) [out] YES 71.01/20.50
Transformed_CSR_innermost_04/MYNAT_nosorts_C.xml 11763389 YES 3.33/3.36 YES 3.83/1.77
Transformed_CSR_innermost_04/MYNAT_nosorts_GM.xml 11763435 YES 38.24/39.78 YES 4.00/1.77
Transformed_CSR_innermost_04/MYNAT_nosorts_iGM.xml 11763354 YES 16.20/17.37 YES 5.16/2.17
Transformed_CSR_innermost_04/MYNAT_nosorts_noand_C.xml 11763420 YES 11.79/12.97 YES 3.85/1.73
Transformed_CSR_innermost_04/MYNAT_nosorts_noand_GM.xml 11763379 YES 62.67/66.37 YES 4.64/2.05
Transformed_CSR_innermost_04/MYNAT_nosorts_noand_iGM.xml 11763345 YES 79.24/80.80 YES 7.53/2.72
Transformed_CSR_innermost_04/OvConsOS_complete_C.xml 11763317 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/OvConsOS_complete_GM.xml 11763409 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/OvConsOS_complete_iGM.xml 11763489 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/OvConsOS_complete_noand_C.xml 11763342 timeout (wallclock) [out] YES 10.08/3.99
Transformed_CSR_innermost_04/OvConsOS_complete_noand_GM.xml 11763344 YES 7.55/7.60 YES 43.55/14.67
Transformed_CSR_innermost_04/OvConsOS_complete_noand_iGM.xml 11763408 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/OvConsOS_nokinds_C.xml 11763482 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/OvConsOS_nokinds_GM.xml 11763412 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/OvConsOS_nokinds_iGM.xml 11763466 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/OvConsOS_nokinds_noand_C.xml 11763424 timeout (wallclock) [out] YES 7.36/2.62
Transformed_CSR_innermost_04/OvConsOS_nokinds_noand_GM.xml 11763330 YES 1.10/1.13 YES 15.43/5.16
Transformed_CSR_innermost_04/OvConsOS_nokinds_noand_iGM.xml 11763421 timeout (wallclock) [out] YES 179.26/63.05
Transformed_CSR_innermost_04/OvConsOS_nosorts_C.xml 11763486 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/OvConsOS_nosorts_GM.xml 11763333 timeout (wallclock) [out] NO 12.41/6.01
Transformed_CSR_innermost_04/OvConsOS_nosorts_iGM.xml 11763472 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/OvConsOS_nosorts_noand_C.xml 11763302 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/OvConsOS_nosorts_noand_GM.xml 11763366 timeout (wallclock) [out] NO 21.36/10.64
Transformed_CSR_innermost_04/OvConsOS_nosorts_noand_iGM.xml 11763290 timeout (wallclock) [out] timeout (wallclock) [out]
Transformed_CSR_innermost_04/PALINDROME_complete_C.xml 11763321 timeout (wallclock) [out] YES 7.51/2.76
Transformed_CSR_innermost_04/PALINDROME_complete_GM.xml 11763367 YES 20.76/20.97 YES 7.83/2.93
Transformed_CSR_innermost_04/PALINDROME_complete_iGM.xml 11763508 YES 37.28/38.02 YES 9.95/3.64
Transformed_CSR_innermost_04/PALINDROME_complete_noand_C.xml 11763495 timeout (wallclock) [out] YES 7.45/2.71
Transformed_CSR_innermost_04/PALINDROME_complete_noand_GM.xml 11763397 YES 7.23/7.23 YES 16.32/9.78
Transformed_CSR_innermost_04/PALINDROME_complete_noand_iGM.xml 11763426 YES 228.15/228.74 YES 16.37/5.91
Transformed_CSR_innermost_04/PALINDROME_nokinds_C.xml 11763355 YES 0.21/0.21 YES 4.11/1.87
Transformed_CSR_innermost_04/PALINDROME_nokinds_GM.xml 11763434 YES 0.83/0.81 YES 3.87/1.76
Transformed_CSR_innermost_04/PALINDROME_nokinds_iGM.xml 11763287 YES 1.20/1.19 YES 6.02/2.31
Transformed_CSR_innermost_04/PALINDROME_nokinds_noand_C.xml 11763277 YES 1.07/1.23 YES 4.99/2.18
Transformed_CSR_innermost_04/PALINDROME_nokinds_noand_GM.xml 11763425 YES 1.21/1.47 YES 6.28/2.37
Transformed_CSR_innermost_04/PALINDROME_nokinds_noand_iGM.xml 11763449 YES 5.09/5.18 YES 15.54/4.83
Transformed_CSR_innermost_04/PALINDROME_nosorts_C.xml 11763362 YES 0.11/0.11 YES 3.55/2.49
Transformed_CSR_innermost_04/PALINDROME_nosorts_GM.xml 11763370 YES 0.28/0.26 YES 3.90/2.16
Transformed_CSR_innermost_04/PALINDROME_nosorts_iGM.xml 11763293 YES 0.20/0.20 YES 4.97/2.32
Transformed_CSR_innermost_04/PALINDROME_nosorts_noand_C.xml 11763441 YES 0.13/0.12 YES 3.71/1.68
Transformed_CSR_innermost_04/PALINDROME_nosorts_noand_GM.xml 11763513 YES 0.29/0.27 YES 3.57/1.58
Transformed_CSR_innermost_04/PALINDROME_nosorts_noand_iGM.xml 11763308 YES 0.29/0.30 YES 5.06/2.03
Transformed_CSR_innermost_04/PEANO_complete_C.xml 11763349 timeout (wallclock) [out] YES 5.52/2.17
Transformed_CSR_innermost_04/PEANO_complete_GM.xml 11763464 YES 14.18/14.82 YES 5.19/2.08
Transformed_CSR_innermost_04/PEANO_complete_iGM.xml 11763444 YES 16.23/17.25 YES 6.26/2.44
Transformed_CSR_innermost_04/PEANO_complete_noand_C.xml 11763442 timeout (wallclock) [out] YES 6.22/2.32
Transformed_CSR_innermost_04/PEANO_complete_noand_GM.xml 11763343 YES 1.95/1.94 YES 11.43/4.03
Transformed_CSR_innermost_04/PEANO_complete_noand_iGM.xml 11763278 YES 117.89/120.84 YES 158.03/63.71
Transformed_CSR_innermost_04/PEANO_nokinds_C.xml 11763475 timeout (wallclock) [out] YES 4.33/1.87
Transformed_CSR_innermost_04/PEANO_nokinds_GM.xml 11763498 YES 1.40/1.59 YES 4.24/2.12
Transformed_CSR_innermost_04/PEANO_nokinds_iGM.xml 11763526 YES 1.78/1.86 YES 5.32/2.08
Transformed_CSR_innermost_04/PEANO_nokinds_noand_C.xml 11763459 timeout (wallclock) [out] YES 4.40/1.82
Transformed_CSR_innermost_04/PEANO_nokinds_noand_GM.xml 11763478 YES 0.28/0.27 YES 7.27/2.77
Transformed_CSR_innermost_04/PEANO_nokinds_noand_iGM.xml 11763422 YES 5.51/5.85 YES 25.03/8.20
Transformed_CSR_innermost_04/PEANO_nosorts_C.xml 11763484 YES 0.20/0.52 YES 3.69/1.78
Transformed_CSR_innermost_04/PEANO_nosorts_GM.xml 11763303 YES 0.18/0.18 YES 7.47/2.17
Transformed_CSR_innermost_04/PEANO_nosorts_iGM.xml 11763518 YES 0.16/0.17 YES 4.90/1.98
Transformed_CSR_innermost_04/PEANO_nosorts_noand_C.xml 11763249 YES 0.28/0.29 YES 3.76/1.73
Transformed_CSR_innermost_04/PEANO_nosorts_noand_GM.xml 11763454 YES 0.22/0.21 YES 3.57/1.59
Transformed_CSR_innermost_04/PEANO_nosorts_noand_iGM.xml 11763288 YES 0.31/0.30 YES 5.44/2.16
Mixed_innermost/bn111.xml 11763189 YES 0.02/0.02 YES 3.67/1.66
Mixed_innermost/cade04.xml 11763188 timeout (wallclock) [out] timeout (wallclock) [out]
Mixed_innermost/cade05.xml 11763197 timeout (wallclock) [out] YES 6.16/2.57
Mixed_innermost/cade12.xml 11763192 timeout (wallclock) [out] timeout (wallclock) [out]
Mixed_innermost/cade13.xml 11763199 timeout (wallclock) [out] YES 6.05/2.53
Mixed_innermost/gkg.xml 11763207 YES 0.01/0.01 YES 3.49/1.77
Mixed_innermost/innermost1.xml 11763204 YES 0.01/0.01 YES 3.48/1.68
Mixed_innermost/innermost2.xml 11763198 timeout (wallclock) [out] YES 3.69/1.67
Mixed_innermost/innermost3.xml 11763185 YES 120.87/121.13 YES 4.29/1.95
Mixed_innermost/innermost4.xml 11763187 YES 122.89/123.17 YES 3.96/1.81
Mixed_innermost/innermost5.xml 11763196 timeout (wallclock) [out] YES 4.11/1.83
Mixed_innermost/muladd.xml 11763201 MAYBE 40.25/40.29 NO 4.69/2.25
Mixed_innermost/n001.xml 11763209 MAYBE 40.72/40.75 NO 6.35/2.54
Mixed_innermost/narrow1.xml 11763206 timeout (wallclock) [out] timeout (wallclock) [out]
Mixed_innermost/narrow2.xml 11763190 timeout (wallclock) [out] timeout (wallclock) [out]
Mixed_innermost/run_again1.xml 11763203 timeout (wallclock) [out] NO 7.64/2.97
Mixed_innermost/run_again2.xml 11763200 timeout (wallclock) [out] timeout (wallclock) [out]
Mixed_innermost/test10.xml 11763194 YES 0.01/0.01 YES 3.77/1.69
Mixed_innermost/test75.xml 11763191 YES 20.15/20.19 YES 4.65/2.42
Mixed_innermost/test76.xml 11763210 YES 0.15/0.17 YES 7.33/3.08
Mixed_innermost/test77.xml 11763202 YES 0.15/0.25 YES 4.38/2.64
Mixed_innermost/test830.xml 11763211 YES 0.03/0.04 YES 3.82/1.72
Mixed_innermost/test833.xml 11763184 YES 0.12/0.15 YES 3.41/1.58
Mixed_innermost/test9.xml 11763208 YES 0.44/0.45 YES 4.12/1.88
Mixed_innermost/thiemann26i.xml 11763193 timeout (wallclock) [out] YES 7.82/2.90
Mixed_innermost/thiemann28i.xml 11763205 timeout (wallclock) [out] YES 8.52/4.74
Mixed_innermost/toyama.xml 11763195 YES 0.01/0.01 YES 6.89/1.66
Mixed_innermost/tricky1.xml 11763186 YES 0.01/0.01 YES 7.31/1.67
Mixed_innermost/wiehe13.xml 11763212 YES 0.63/0.63 YES 6.04/2.32
Mixed_innermost/wiehe14.xml 11763213 YES 0.50/0.51 YES 6.74/2.46
213 300